AI20P RTL Engineer

QpiSemi; Bengaluru; Sur place; INR 1 500 000 - 2 800 000; Plein temps

Résumé du poste

QpiSemi seeks a skilled RTL designer in Bengaluru to push the boundaries of AI accelerators by drafting RTL in SystemVerilog and shaping microarchitectures. You will collaborate across teams to deliver high-performance, timing-critical designs and work closely with DV and physical design groups to optimize for timing, area, and power.

The role requires a Bachelor’s in engineering or related field and 3+ years of ASIC RTL experience, with strong SystemVerilog and scripting skills

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 3+ years of experience in high-performance ASIC RTL design, including clocking, reset, and timing-critical development.
• Proficiency in SystemVerilog and digital design fundamentals (e.g., synchronous/asynchronous logic, state machines).
• Experience using scripting languages like Python, Tcl, or Perl for design automation and data analysis.
• Strong track record of cross-functional collaboration with software, hardware, and architecture teams.

Responsabilités

• Define and document complex microarchitecture for TPU compute, networking, or control subsystems.
• Develop performant, power-efficient, and synthesizable RTL code in SystemVerilog.
• Collaborate with DV team to create test plans, debug RTL, and ensure functional correctness.
• Partner with physical design teams to optimize logic for timing, area, power, and manufacturability.
• Evaluate design features and hardware capabilities with architecture and power teams.
• Contribute to internal design methodologies and automation flows.

Connaissances

SystemVerilog

Digital design fundamentals

State machines

Clocking & timing

Formation

Bachelor's degree in Electrical Engineering

Outils

Python

Tcl

Perl

Description du poste

Join a cutting-edge hardware development team to push the boundaries of Machine Learning by designing the Register-Transfer Level (RTL) for custom AI accelerators. You will co-design microarchitectures and write high-quality RTL code, shaping the next generation of computing infrastructure.

Core Responsibilities

• Microarchitecture & Design: Define and document complex microarchitecture for TPU compute, networking, or control subsystems.
• RTL Development: Develop performant, power-efficient, and synthesizable RTL code in SystemVerilog.
• Verification Collaboration: Work closely with the Design Verification (DV) team to create test plans, debug RTL, and ensure functional correctness.
• Physical Design Co-design: Partner with physical design teams to optimize logic for timing, area, power, and manufacturability.
• Architecture & Power: Evaluate design features and hardware capabilities alongside architecture and power teams.
• Tooling: Contribute to the continuous enhancement of internal design methodologies and automation flows.

Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Experience: 3+ years of experience in high-performance ASIC RTL design, including clocking, reset, and timing-critical development.
• Technical Skills: Proficiency in SystemVerilog and digital design fundamentals (e.g., synchronous/asynchronous logic, state machines).
• Automation: Experience using scripting languages like Python, Tcl, or Perl for design automation and data analysis.
• Teamwork: Strong track record of cross-functional collaboration with software, hardware, and architecture teams.