RTL Design Engineer

TylSemi; Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

TylSemi in Bengaluru, Karnataka is seeking a talented RTL Design Engineer to join our semiconductor design team. The role involves designing and developing high-performance digital IPs and SoC components for AI and HPC applications.

Successful candidates will have experience in RTL design, a solid educational background, and a passion for semiconductor innovation. This position offers the opportunity to work in a collaborative environment with a focus on delivering high-quality silicon.

Qualifications

• Bachelor’s or master’s degree in electrical engineering, electronics engineering, computer engineering, or a related field.
• Experience in RTL design and digital IC development.
• Strong understanding of digital design fundamentals and computer architecture.

Responsibilities

• Develop RTL designs using Verilog/SystemVerilog based on specifications.
• Collaborate with cross-functional teams throughout the ASIC development lifecycle.
• Analyze synthesis results and optimize timing, power, and area.

Skills

RTL Design

Digital IC Development

Problem-solving

Verilog/SystemVerilog

Collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Simulation Tools

Synthesis Tools

FPGA Prototyping

Job description

My name is TylSemi Solutions Private Limited, and we are looking for a talented RTL Design Engineer to join our semiconductor design team. You will design and develop high‑performance digital IPs and SoC components for AI, HPC, and networking applications, collaborating with architecture, verification, physical design, and software teams to deliver robust silicon solutions.

What You’ll Do

• Develop RTL designs using Verilog/SystemVerilog based on architectural and micro‑architecture specifications.
• Participate in micro‑architecture definition and design reviews.
• Implement high‑performance, area‑efficient, and power‑optimized digital logic.
• Develop and maintain design documentation, specifications, and implementation guidelines.
• Collaborate with verification engineers to define verification strategies and debug functional issues.
• Perform RTL simulations and support design validation activities.
• Analyze synthesis results and work with physical design teams to optimize timing, power, and area.
• Support SoC integration activities and resolve integration‑related issues.
• Participate in design reviews, code reviews, and quality improvement initiatives.
• Work closely with cross‑functional teams throughout the ASIC development lifecycle.

Required Qualifications

• Bachelor’s or master’s degree in electrical engineering, electronics engineering, computer engineering, or a related field.
• Experience in RTL design and digital IC development.
• Strong understanding of digital design fundamentals, computer architecture, and ASIC design flow.
• Proficiency in RTL design and coding methodologies, logic design and finite state machines (FSMs), clock‑domain crossing (CDC) concepts, simulation and debugging tools, and synthesis and timing analysis concepts.
• Strong analytical and problem‑solving skills.

Preferred Qualifications

• Experience designing IPs or subsystems for AI, HPC, networking, or data‑center applications.
• Knowledge of industry‑standard protocols such as DDR, Ethernet, and CXL.
• Familiarity with scripting languages such as Python, Perl, Shell, or TCL.
• Exposure to low‑power design methodologies and power intent formats (UPF/CPF).
• Understanding of linting, CDC, RDC, and formal verification tools.
• Experience with FPGA prototyping.

Key Attributes

• Strong attention to detail and commitment to design quality.
• Passion for semiconductor innovation and cutting‑edge technologies.
• Excellent debugging and problem‑solving abilities.
• Ability to work effectively in a collaborative and fast‑paced environment.
• Strong communication and teamwork skills.
• Ownership mindset with a focus on delivering high‑quality silicon.

About TylSemi: We build the chiplet infrastructure IP—IO, power delivery, and interconnect building blocks—that enables AI and HPC systems to scale.