AI20P Design Verification Engineer

Qpisemi; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Qpisemi in Bengaluru, India, is seeking an experienced hardware verification engineer to validate RTL for ASICs/FPGAs. You will design and implement constrained-random testbenches using SystemVerilog and UVM, drive verification planning, and lead coverage analysis.

Applicants should have 5+ years of RTL verification, expertise with Synopsys VCS or Cadence Xcelium, and strong debugging skills. Familiarity with AI/ML accelerator verification is a plus.

Qualifications

• 5+ years RTL verification for ASICs or FPGAs.
• SystemVerilog and UVM experience.
• Experience with VCS or Xcelium and regression systems.

Responsibilities

• Define test plans and verify critical scenarios.
• Develop and maintain constrained-random testbenches.
• Analyze coverage and close holes.
• Debug RTL bugs and iterate tests.
• Innovate verification flows and build automation.

Skills

SystemVerilog

UVM

RTL verification

Python scripting

Debugging

Testbench design

Coverage analysis

Education

Bachelor's in EE/CE/CS

Master’s or PhD (preferred)

Tools

Synopsys VCS

Cadence Xcelium

Job description

Join the hardware engineering team building the next generation of custom silicon that powers breakthrough AI/ML models and hyperscale cloud services. In this role, you will leverage your digital verification expertise to validate complex TPU microarchitectures, ensuring zero-bug functionality before tape-out.

Key Responsibilities

• Verification Planning: Collaborate with microarchitecture and design teams to understand specifications and define comprehensive test plans targeting critical operational and corner-case scenarios.
• Testbench Development: Architect, build, and maintain scalable, constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Coverage Analysis: Define, track, and close functional and code coverage metrics to identify verification holes and guarantee rigorous testing.
• Debugging & Problem Solving: Work closely with design engineers to debug failing tests, root-cause RTL bugs, and iterate on test cases.
• Methodology Innovation: Optimize verification flows, build regression systems, and develop automation scripts (e.g., Python or Perl) to increase verification throughput and efficiency.

Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.
• Experience: 5+ years of experience verifying digital logic at the RTL level for ASICs or FPGAs.
• Methodologies: Deep expertise in industry-standard verification methodologies including SystemVerilog and UVM.
• Environment Tools: Experience with industry-standard simulators (e.g., Synopsys VCS, Cadence Xcelium) and regression systems.

Preferred Qualifications

• Education: Master’s degree or PhD in Electrical Engineering or Computer Science, with a heavy emphasis on computer architecture.
• Domain Knowledge: Direct experience verifying AI/ML Accelerators, GPUs, or highly parallel vector processing units.
• Advanced Debugging: Familiarity with formal verification tools/languages (e.g., SVA - SystemVerilog Assertions).
• Software/Scripting: Proficiency in scripting and automation using Python or Shell/Bash.