Senior RTL Digital Design Engineer - Data Center & Energy

Analog Devices; Limerick; On-site; EUR 85,000 - 120,000; Full time

Job summary

Analog Devices, in Limerick, Ireland, seeks a Senior Digital Design Engineer for the Data Center & Energy group. You will implement and verify RTL for mixed-signal SoCs, focusing on synthesis, timing closure, and DFT insertion while collaborating with analog, firmware, and validation teams.

The role requires a BS in Electrical or Computer Engineering, 4+ years in ASIC/SoC digital design, and strong Verilog/SystemVerilog skills; FPGA prototyping and power-system familiarity are a plus.

Qualifications

• BS in Electrical or Computer Engineering (or equivalent).
• 4+ years of experience in ASIC/SoC digital design.
• Proficiency in Verilog/SystemVerilog and scripting languages (Python, C).
• Familiarity with RTL-to-GDS flows (Genus, Innovus, Tempus, Conformal).
• Understanding of DFT concepts and basic test strategies.
• Working knowledge of analog circuit operation and lab practices.
• Strong problem-solving skills and ability to work independently with minimal supervision.
• Good organization; written and verbal communication skills.

Responsibilities

• Develop and verify RTL for digital blocks and subsystems; ensure functional correctness and timing closure
• Perform synthesis, static timing analysis, and support design-for-test (DFT) insertion and pattern generation
• Collaborate with analog, firmware, and validation teams to integrate digital content into mixed-signal SoCs
• Assist with silicon bring-up and debug; support lab measurements and correlation to simulation
• Contribute to methodology improvements and automation initiatives

Skills

Verilog/SystemVerilog

Python

C

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Genus

Innovus

Tempus

Conformal

Job description

Analog Devices, in Limerick, Ireland, seeks a Senior Digital Design Engineer for the Data Center & Energy group. You will implement and verify RTL for mixed-signal SoCs, focusing on synthesis, timing closure, and DFT insertion while collaborating with analog, firmware, and validation teams.

The role requires a BS in Electrical or Computer Engineering, 4+ years in ASIC/SoC digital design, and strong Verilog/SystemVerilog skills; FPGA prototyping and power-system familiarity are a plus.