Senior Digital Design Engineer, Data Center & Energy

1020 ADBV Ireland; Limerick; On-site; EUR 90,000 - 120,000; Full time

Job summary

Analog Devices, Inc. in Limerick, Ireland seeks a Senior Digital Design Engineer for its Data Center & Energy group. You will develop and verify RTL for digital blocks in mixed-signal SoCs, ensuring timing closure and testability.

Collaboration with analog, firmware, and validation teams is essential for robust, manufacturable solutions. The role requires 4+ years in ASIC/SoC digital design, strong Verilog/SystemVerilog, and experience with RTL-to-GDS flows.

Qualifications

• BS in Electrical or Computer Engineering (or equivalent).
• 4+ years of experience in ASIC/SoC digital design.
• Proficiency in Verilog/SystemVerilog and scripting languages (Python, C).
• Familiarity with RTL-to-GDS flows (Genus, Innovus, Tempus, Conformal).
• Understanding of DFT concepts and basic test strategies.
• Working knowledge of analog circuit operation and lab practices.
• Strong problem‑solving skills and ability to work independently with minimal supervision.
• Good organization; written and verbal communication skills.

Responsibilities

• Develop and verify RTL for digital blocks and subsystems.
• Ensure functional correctness and timing closure.
• Perform synthesis, static timing analysis, and support design-for-test (DFT) insertion and pattern generation.
• Collaborate with analog, firmware, and validation teams to integrate digital content into mixed-signal SoCs.
• Assist with silicon bring-up and debug; support lab measurements and correlation to simulation.
• Contribute to methodology improvements and automation initiatives.

Skills

Verilog/SystemVerilog

Python

C

RTL design

DFT

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Genus

Innovus

Tempus

Conformal

Job description

Analog Devices, Inc. in Limerick, Ireland seeks a Senior Digital Design Engineer for its Data Center & Energy group. You will develop and verify RTL for digital blocks in mixed-signal SoCs, ensuring timing closure and testability.

Collaboration with analog, firmware, and validation teams is essential for robust, manufacturable solutions. The role requires 4+ years in ASIC/SoC digital design, strong Verilog/SystemVerilog, and experience with RTL-to-GDS flows.