Senior RFIC Design Engineer — Analog & RX/TX Blocks

Berkley Group; Cork; On-site; EUR 70,000 - 100,000; Part time

Job summary

Berkley Group seeks a Senior RFIC Design Engineer for a 6-month contract in Ireland. You will design and verify RFIC/analogue blocks within Rx/Tx chains, simulate dense sub-cells, and collaborate with layout teams to ensure compliant implementations.

You will validate registers and perform post-layout parasitic analysis to refine designs. Ideal candidates have 5+ years in RFIC design, CMOS/analogue IC experience, and hands-on Cadence ADE/XL, Maestro, Spectre/SpectreRF, AMS, and Verilog-A

Qualifications

• 5+ years of hands-on RFIC design experience.
• Expertise in RFIC and analogue IC design with complex sub-cells.
• CMOS IC design and analogue circuit design experience.
• Hands-on Cadence toolset: ADE/XL and Maestro.
• Strong Spectre/SpectreRF and AMS simulation experience.
• Verilog-A modelling for analogue/RF.
• Rx/Tx chain verification and post-layout parasitic analysis.

Responsibilities

• Design, simulate, and verify RFIC and analogue blocks in a full Rx/Tx signal chain.
• Translate specifications into robust circuit designs.
• Schematic design and verification against technical specs.
• Carry out Rx/Tx chain verification between RF and IF ports.
• Perform top-level verification and reporting of compliance to specs.
• Validate device register controls for testing and verification.
• Collaborate with layout engineers to ensure correct implementation.
• Perform post-layout parasitic simulations and adjust designs.
• Present designs during block-level technical reviews with leads.
• Deliver fully verified blocks and troubleshoot problems in constrained environments.

Skills

RFIC design

Analogue IC design

CMOS IC design

Verilog-A modelling

Rx/Tx verification

Cross-functional teamwork

Tools

Cadence ADE/XL

Maestro

Spectre

SpectreRF

Job description

Berkley Group seeks a Senior RFIC Design Engineer for a 6-month contract in Ireland. You will design and verify RFIC/analogue blocks within Rx/Tx chains, simulate dense sub-cells, and collaborate with layout teams to ensure compliant implementations.

You will validate registers and perform post-layout parasitic analysis to refine designs. Ideal candidates have 5+ years in RFIC design, CMOS/analogue IC experience, and hands-on Cadence ADE/XL, Maestro, Spectre/SpectreRF, AMS, and Verilog-A