Senior Analog RF/IF Design Engineer

European Tech Recruit; Ireland; On-site; EUR 70,000 - 100,000; Full time

Job summary

European Tech Recruit is seeking a Senior Analog Design Engineer to own analogue block design, simulation, verification and delivery, with a focus on full Rx/Tx chain verification between RF and IF ports. You will drive the complete design flow from specification through layout oversight to top-level verification.

The role requires 4–8 years of hands-on experience designing analogue sub-cells and conducting circuit simulations, including post-layout parasitics and design verification against

Qualifications

• 4–8 years of relevant engineering experience.
• Experience designing complex analogue sub-cells and small subsystems.
• Experience with schematic design and circuit simulation.
• Experience with post-layout parasitic simulation.
• Experience performing design verification and reporting compliance against specifications.
• Experience with Rx/Tx chain verification simulations.
• Experience working between RF and IF interfaces.

Responsibilities

• Review analogue block specifications and translate requirements into design activity.
• Perform schematic design and simulation for analogue blocks.
• Oversee physical layout completion with layout engineers.
• Conduct post-layout parasitic simulations and iterate designs as needed.
• Collaborate with technical leads to integrate completed designs.
• Run top-level verification simulations across full Rx/Tx chains between RF and IF ports.

Skills

Analogue design

Schematic design

Circuit simulation

Post-layout parasitic simulation

Rx/Tx chain verification

RF to IF interfaces

Design verification & compliance

Job description

European Tech Recruit is seeking a Senior Analog Design Engineer to own analogue block design, simulation, verification and delivery, with a focus on full Rx/Tx chain verification between RF and IF ports. You will drive the complete design flow from specification through layout oversight to top-level verification.

The role requires 4–8 years of hands-on experience designing analogue sub-cells and conducting circuit simulations, including post-layout parasitics and design verification against