Senior Power Integrity Engineer, SoC PDN/EMIR

Qualcomm

Cork

Hybrid

EUR 70,000 - 110,000

Full time

12 days ago
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Benefits offered by this job

Salary + bonus
Stock options
Pension plan
Education assistance
Relocation support
Insurance

Job summary

QT Technologies Ireland Limited in Cork seeks a PDN/EMIR Engineer to execute power integrity analyses including IR-drop and electromigration for complex ASICs. You will drive PDN closure with cross-functional teams to ensure robust power networks and sign-off across multi-core SOC designs.

Responsibilities cover developing PDN techniques, integrating with RTL-to-GDS flows, and advancing automation for data processing, while collaborating with Physical Design and STA groups to meet Vmin targets

Qualifications

  • 4+ years of ASIC design/verification/validation experience or equivalent.
  • Experience with PDN analysis and sign-off processes.
  • Knowledge of RTL-to-GDS design flows and power integrity sign-off criteria.

Responsibilities

  • Performing PDN checks such as IR-drop, ESD and electromigration for complex cores and full-chip SOCs.
  • Developing new techniques for PDN analyses, optimization and sign-off.
  • Working with design teams on selecting use-cases for PDN sign-off and power analysis on PD gate nets.
  • Collaborating with Physical Design and STA teams for Vmin assessment and optimization.
  • Ensuring PDN sign-off checklist compliance.
  • Automation for power and PDN data mining and processing.
  • Resolving PDN issues across all development phases to ensure project progress.

Skills

Power integrity
IR-drop
Electromigration
Python
TCL
Perl
Automation
PDN sign-off
RD/PHYS
RC/STA tooling

Education

Bachelor's degree in Science/Engineering
Master's degree in Science/Engineering
PhD in Science/Engineering

Tools

RedHawk
RHSC
Voltus
PTPX

Job description

QT Technologies Ireland Limited in Cork seeks a PDN/EMIR Engineer to execute power integrity analyses including IR-drop and electromigration for complex ASICs. You will drive PDN closure with cross-functional teams to ensure robust power networks and sign-off across multi-core SOC designs.

Responsibilities cover developing PDN techniques, integrating with RTL-to-GDS flows, and advancing automation for data processing, while collaborating with Physical Design and STA groups to meet Vmin targets

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