Power Integrity Design Engineer: PDN/EMIR for SoCs

Qualcomm

Ballyerra

On-site

EUR 75,000 - 110,000

Full time

12 days ago

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Benefits offered by this job

Salary bonus

Maternity/paternity leave

Employee stock purchase scheme

Pension matching

Education assistance

Relocation support

Insurance (Life/Medical/Travel)

Job summary

QT Technologies Ireland Limited in Cork seeks an experienced Qualcomm PDN/EMIR Engineer to perform power integrity analyses such as IR-drop and electromigration for high-performance SOCs. You will collaborate with cross-functional teams to ensure PDN closure and sign-off, contributing to robust, low-power ASIC solutions.

The PDN team evaluates block- and top-level power integrity and works with design and Physical Design teams to meet Vmin specs.

Qualifications

Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design/verification/validation experience
Master's degree in Science, Engineering, or related field with 3+ years of related experience
PhD in Science, Engineering, or related field with 2+ years of related experience

Responsibilities

Perform PDN checks such as IR-drop, ESD and electromigration for complex cores and full-chip SOCs
Develop new techniques and methodologies for PDN analyses, optimization and sign-off
Work with design teams on selecting use-cases for PDN sign-off and analyze PD gate netlists
Collaborate with Physical Design and STA teams for Vmin assessment and optimization
Ensure compliance with power integrity signoff checklists and criteria
Automate power and PDN data mining and processing
Anticipate and resolve PDN issues across all development phases