Senior NPU AI Hardware Verification Engineer

Intel Corporation; Leixlip; On-site; EUR 77,000 - 120,000; Full time

Job summary

Intel Corporation in Leixlip, Ireland, seeks a Sr Deep Learning Hardware Verification Engineer to validate next‑generation NPU silicon and optimize AI accelerators. You will join the NPU Hardware Pre‑Silicon Validation team, collaborating with design and AI architects to ensure robust verification across IP portfolios.

The role requires 8+ years in pre‑silicon validation, SystemVerilog/UVM experience, testbench development, and cross‑functional teamwork to shape the AI product roadmap.

Qualifications

• Bachelor's degree in Electronic, Computer Engineering, Computer Science or a related field.
• 8+ years of relevant industry experience in pre‑silicon validation of IPs, ASIC, SoC, or FPGA designs.
• Fully proficient with industry standard verification tools and methodologies (SystemVerilog, VCS, UVM, OVM).
• Experience developing testbenches, test plans, and verification environments.
• Proven track record of signing off complex designs through coverage closure and related techniques.

Responsibilities

• Functional Verification of digital design blocks on Intel's NPU AI accelerators.
• Architect, develop and implement verification environments from planning to signoff.
• Develop test plans and test cases.
• Implement random test generators, BFMs, constraints, checkers and scoreboards.
• Create software-based test cases for AI accelerator validation.
• Collaborate with cross-functional teams to address next‑generation AI requirements.

Skills

SystemVerilog

VCS

UVM/OVM

Testbenches

Communication

Leadership

Education

Bachelor's degree in Electronics/Computer Engineering/CS

Tools

Git

CI pipelines

OpenCV

Job description

Intel Corporation in Leixlip, Ireland, seeks a Sr Deep Learning Hardware Verification Engineer to validate next‑generation NPU silicon and optimize AI accelerators. You will join the NPU Hardware Pre‑Silicon Validation team, collaborating with design and AI architects to ensure robust verification across IP portfolios.

The role requires 8+ years in pre‑silicon validation, SystemVerilog/UVM experience, testbench development, and cross‑functional teamwork to shape the AI product roadmap.