Senior Verification Engineer

Intel; Leixlip; Presencial; EUR 75 000 - 118 000; Tempo integral

Resumo da oferta

Intel in Ireland (Leixlip) seeks a Senior IP Design Verification Engineer to lead verification of ASIC/SOC/IP blocks for NIC, IPU and AI domains. You will design verification plans, build test benches, and drive environments to validate IPs using SystemVerilog, UVM and formal methods, mentoring engineers and adopting AI-assisted flows.

Join Intel's Central Engineering Group delivering high-performance silicon, collaborating with architecture, design and software teams to meet strict performance

Qualificações

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 10+ years of experience in functional design verification of ASIC, SOC or FPGA designs with SystemVerilog, OVM/UVM, and debugging tools.
• Proficiency in creating IP test environments and/or using formal verification methods.
• Strong knowledge of digital design fundamentals and microarchitecture principles.

Responsabilidades

• Own verification planning and execution for key IP features across IP and subsystem integration points.
• Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models.
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality.
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics.
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams.
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows.
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality.
• Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral

Conhecimentos

System Verilog

OVM/UVM

Debugging tools

Digital design fundamentals

Microarchitecture

Formal verification

Networking protocols

AMBA APB/AXI

SystemC / Python / Perl / Shell

AI-assisted verification

Formação académica

Bachelor's degree in Electrical/Computer Engineering or related field

Master's or PhD in Electrical/Computer Engineering or related field

Descrição da oferta de emprego

Job Description:

The Role and Impact

You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As a senior IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will technically lead teams in developing verification plans, creating test benches, and building environments to thoroughly validate meaningful parts of the chip - complex IPs and subsystems. Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow - planning, stimulus and checker development, coverage analysis, debug and more.

Business group

You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products. The group produces innovative technologies and solutions for hyperscalers, cloud providers, networking, AI and other specialized workloads. As part of this dynamic team, you will contribute to Intel's commitment to advancing silicon and system innovation.

Key Responsibilities

• Own verification planning and execution for key IP features across IP and subsystem integration points
• Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
• Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10+ years of experience in functional design verification of ASIC, SOC or FPGA designs with expertise in System Verilog, OVM/UVM, and debugging tools.
• Proficiency in creating IP test environments and/or using formal verification methods
• Strong knowledge of digital design fundamentals and microarchitecture principles.

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with relevant experience in design verification.
• Experience with formal property verification, System Verilog Assertions, code and functional coverage implementation and analysis
• Experience collaborating across teams to drive architectural improvements.
• Use of AI tools would be an advantage. At a minimum, require someone that is passionate about performing Pre-Silicon DV harnessing the power of AI.
• Experience with switching/routing and communications protocols such as Ethernet, and Cryptographic Protocols such IPSec, DTLS and MACSec.
• Experience with AMBA protocols such as APB and AXI.
• Experience with languages such as SystemC, Python, Perl, Shell scripting and how AI can be used to integrate these in verification flows.

We invite you to bring your leadership, expertise and enthusiasm to a team where your contributions will drive technological progress and create opportunities for impactful learning and growth.

Job Type:

Experienced Hire

Shift:

Shift 1 (Ireland)

Primary Location:

Ireland, Leixlip

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

EU Salary

We offer a total compensation package that ranks among the best in the industry.

Annual Salary Range for this job which could be performed in Ireland is: 75,200.00 € - 117,500.00 €

The compens