Senior DDR Memory Controller Architect

Cadence Design Systems, Inc.; Cork; On-site; EUR 120,000 - 180,000; Full time

Job summary

Cadence Design Systems, Inc. in Cork, Ireland, is seeking a Principal Design Engineer (Memory) to join our Controller IP team. You will architect DDR controller features, design RTL, and collaborate across Verification, Support, and Delivery to advance our products.

Ideal candidates have 10+ years in microelectronics/EDA, strong Verilog RTL and MDV experience, and leadership capabilities. This role is on-site in Cork with opportunities to influence a global IP program.

Qualifications

• Degree in Electrical/Electronic Engineering or related discipline.
• 10+ years’ experience in microelectronics/EDA industry.
• Experience of Verilog RTL Design essential.
• Experience of Metric Driven Verification (MDV) essential.
• Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
• Experience of SoC Architecture and Development essential.
• Experience of Technical Team leadership essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal, and communication skills.

Responsibilities

• Architect solutions for the latest DDR controller features and customer requirements.
• Design RTL in a highly configurable and automated environment.
• Work in small project teams.
• Work across disciplines with Design Verification, Support, Delivery, Application Engineers, PHY design team, etc.
• Utilize Cadence’s Design Automation flow and IP development tools.
• Develop high speed circuits and low power features.
• Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.
• Participate in an engineering team to advance our product.

Skills

Verilog RTL Design

MDV

SoC Architecture

Technical Team Leadership

Communication

English Proficiency

Education

Degree in Electrical/Electronic Engineering

Tools

LINT

Synthesis

CDC Analysis

SystemVerilog

Cadence Design Automation

Job description

Cadence Design Systems, Inc. in Cork, Ireland, is seeking a Principal Design Engineer (Memory) to join our Controller IP team. You will architect DDR controller features, design RTL, and collaborate across Verification, Support, and Delivery to advance our products.

Ideal candidates have 10+ years in microelectronics/EDA, strong Verilog RTL and MDV experience, and leadership capabilities. This role is on-site in Cork with opportunities to influence a global IP program.