Senior Design & RTL Engineering Leader (Cork)

Cadence Design Systems; Cork; On-site; EUR 150,000 - 190,000; Full time

Job summary

Cadence Design Systems in Cork, Ireland seeks a Sr Design Engineering Manager to lead RTL/IP development and coordinate architecture with system architects for cutting-edge IP such as UCIe, Ethernet, and PCIe. Based in Cork, you will drive technical direction and sign‑off for IP releases while mentoring senior engineers.

The role requires extensive microelectronics experience, strong leadership, and excellent English communication.

Qualifications

• Degree in Electrical/Electronic Engineering or microelectronics.
• 15-20 years’ experience in microelectronics industry.
• Expert in Verilog/SystemVerilog RTL design.
• Expert in front-end tools covering LINT, synthesis, CDC/RDC analysis.
• Experience of SoC architecture and development.
• Experience of technical team leadership.
• Excellent oral and written English.

Responsibilities

• Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe.
• Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe.
• Hands‑on leadership of RTL development from micro‑architecture definition to IP sign‑off for general release.
• Contribute to planning of activities and milestones for the digital development teams.
• Leadership of cross‑functional technical meetings with Analog & Software counterparts.
• Support customer pre‑sales and post‑sales meetings.
• Develop, maintain and improve processes and procedures for efficient product execution, IP quality and industry best practices.
• Participate in Technical Review Meetings and Checklist Reviews as part of ISO‑9001.
• Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI‑SIG, JEDEC, UCIe.
• Represent Cadence by presenting at Industry Conference such as IEEE, DAC.

Skills

Verilog/SystemVerilog RTL

Front-end design tools

SoC architecture

Technical leadership

English proficiency

Education

Electrical/Electronic Engineering or microelectronics degree

Tools

LINT

Synthesis

CDC/RDC analysis

Job description

Cadence Design Systems in Cork, Ireland seeks a Sr Design Engineering Manager to lead RTL/IP development and coordinate architecture with system architects for cutting-edge IP such as UCIe, Ethernet, and PCIe. Based in Cork, you will drive technical direction and sign‑off for IP releases while mentoring senior engineers.

The role requires extensive microelectronics experience, strong leadership, and excellent English communication.