Senior ASIC Verification Engineer - UVM & SystemVerilog

European Tech Recruit; Cork; On-site; EUR 60,000 - 90,000; Full time

Job summary

European Tech Recruit is partnering with a leading technology innovator in Cork, Ireland, to hire an experienced Verification Engineer. You will apply UVM, formal verification, and constrained‑random techniques to verify ASICs and ensure tapeout‑quality sensor algorithms.

Responsibilities include building RTL testbenches, C models, SystemVerilog assertions, Python automation, and regression frameworks. You will collaborate across design, systems and software teams and contribute to documentation

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• 3+ years in ASIC verification or similar roles.
• Proficiency in UVM and SystemVerilog (including SVAs).
• Experience with constrained-random verification and coverage-driven verification.

Responsibilities

• Apply UVM and formal verification methodologies.
• Develop testbenches and verification components (UVCs, C models, vertical/horizontal envs).
• Perform RTL verification of sensor algorithms for tapeout-quality delivery.
• Create test plans based on design specs; collaborate with design and systems teams.
• Integrate C models within UVM-based verification frameworks.
• Develop SystemVerilog assertions to validate design correctness.
• Debug, verify, and optimize designs to meet reference test vectors.
• Analyze coverage metrics and close gaps with design teams.
• Develop and enhance regression frameworks; debug regression failures with cross‑functional teams.
• Support subsystem integration, including test planning, vector delivery, and debugging.
• Build Python-based automation to improve workflows and efficiency.
• Participate in project reviews and provide technical input.

Skills

Analytical thinking

Team collaboration

Problem solving

Excellent communication

Education

Bachelor's degree in Science/Engineering

Tools

UVM

SystemVerilog

RTL simulation tools

Python

C/C++

Job description

European Tech Recruit is partnering with a leading technology innovator in Cork, Ireland, to hire an experienced Verification Engineer. You will apply UVM, formal verification, and constrained‑random techniques to verify ASICs and ensure tapeout‑quality sensor algorithms.

Responsibilities include building RTL testbenches, C models, SystemVerilog assertions, Python automation, and regression frameworks. You will collaborate across design, systems and software teams and contribute to documentation