Senior Analog IP Architect - Power, Clock & PLLs

onsemi; Cork; On-site; EUR 120,000 - 180,000; Full time

Job summary

onsemi is seeking an Analog Design Architect to shape architecture, strategy and roadmaps for power, clock, monitoring and reset IP for the Treo platform in BCD65. You will translate product needs into coherent IP architectures and lead multi-generation roadmaps while guiding teams through verification and production readiness.

You will mentor junior engineers, contribute to high-risk circuits, and champion reusable IP and standardized interfaces across the platform.

Qualifications

• Degree in electrical/electronic engineering with extensive analog IC design experience (15+ years or 8+ years with Master's).
• Strong IP architecture and hands-on design experience with bandgap references, LDOs, DC–DC regulators, oscillators and PLLs.

Responsibilities

• Define and evolve architecture and technical strategy for Treo BCD65 IP portfolio.
• Translate product needs into architecture requirements and multi-generation roadmaps.
• Lead architectural trade-off studies and guide engineering through verification and production readiness.

Skills

Analog IP architecture

Circuit design

Mentoring

AI-assisted design

Education

Bachelor's or Master’s in Electrical Engineering

Job description

onsemi is seeking an Analog Design Architect to shape architecture, strategy and roadmaps for power, clock, monitoring and reset IP for the Treo platform in BCD65. You will translate product needs into coherent IP architectures and lead multi-generation roadmaps while guiding teams through verification and production readiness.

You will mentor junior engineers, contribute to high-risk circuits, and champion reusable IP and standardized interfaces across the platform.