Senior Analog IC Design Engineer - Power & Clock IP

onsemi; Cork; On-site; EUR 90,000 - 120,000; Full time

Job summary

onsemi seeks an Analog IC Designer to join its Core Analog IP Development Centre of Excellence in Cork, Ireland. You will design and develop analog IP for the Treo platform, including bandgap references, LDOs, DC–DC regulators, oscillators and PLLs, and mentor junior engineers.

Responsibilities include transistor‑level design, cross‑process verification, and post‑layout validation to ensure IP meets performance goals and can be reused across the platform.

Qualifications

• Bachelor’s degree in electrical or electronic engineering or a closely related discipline (minimum 8 years analog IC design experience)
• Master’s degree in a relevant discipline with at least 4 years of analog IC design experience preferred
• Hands-on design experience with bandgap references, LDOs, DC–DC regulators, oscillators and PLLs
• Strong analog circuit fundamentals and post-layout verification
• Experience mentoring junior engineers and driving designs through to mass production

Responsibilities

• Contribute to development of power, clock, monitoring and reset IP for the Treo BCD65 platform.
• Engage with product-line teams to understand requirements and constraints.
• Translate needs into IP specifications and roadmaps for Core Analog teams.
• Design and verify analog IP from specification to silicon characterization.
• Collaborate with layout engineers on matching, parasitics and reliability.
• Provide technical guidance and mentoring to junior engineers.

Skills

Analog IC design

Transistor-level design

Circuit simulation

Layout collaboration

Silicon characterization

Mentoring

Technical leadership

Education

Bachelor’s degree in electrical or electronic engineering

Master’s degree in a relevant discipline

Job description

onsemi seeks an Analog IC Designer to join its Core Analog IP Development Centre of Excellence in Cork, Ireland. You will design and develop analog IP for the Treo platform, including bandgap references, LDOs, DC–DC regulators, oscillators and PLLs, and mentor junior engineers.

Responsibilities include transistor‑level design, cross‑process verification, and post‑layout validation to ensure IP meets performance goals and can be reused across the platform.