GPU CAD Engineer: RTL-to-GDS PPA Enhancements

MaC VC; Cork; On-site; EUR 90,000 - 150,000; Full time

Benefits offered by this job

Salary bonus

Stock options

Matching pension

Education assistance

Relocation support

Life and health insurance

Employee clubs

Job summary

Qualcomm Cork-based team seeks a skilled engineer to advance GPU core design, from RTL through GDSII, focusing on power, performance and area improvements. You will work with RTL/ASIC flows and verification to optimize PPA and collaborate across design, power, and post‑silicon teams.

The role requires Verilog/SystemVerilog expertise, RTL synthesis, and experience with Synopsys tools such as Fusion Compiler, RTL Architect, PrimeTime, and ECO methods.

Qualifications

• Knowledge of RTL to GDSII flow.
• Experience with ASIC design/verification flows.
• Hands-on with EDA tools and scripting.
• Ability to optimize power, performance, area.

Responsibilities

• Develop and improve GPU core flows from RTL to GDSII.
• Collaborate with design/verification teams to drive PPA improvements.
• Identify flow and methodology improvements and implement fixes.

Skills

RTL design

Verilog

SystemVerilog

RTL synthesis

Design constraints

Clock Tree Analysis

ECO methods

Python

UNIX shell

PPA optimization

Education

Bachelor's in Science/Engineering

Master's in Science/Engineering

PhD in Science/Engineering

Tools

Synopsys Fusion Compiler

Synopsys RTL‑Architect

PrimePower

PrimeTime

Prime Closure

Job description

Qualcomm Cork-based team seeks a skilled engineer to advance GPU core design, from RTL through GDSII, focusing on power, performance and area improvements. You will work with RTL/ASIC flows and verification to optimize PPA and collaborate across design, power, and post‑silicon teams.

The role requires Verilog/SystemVerilog expertise, RTL synthesis, and experience with Synopsys tools such as Fusion Compiler, RTL Architect, PrimeTime, and ECO methods.