Ultra-Low Latency C++ Lead Engineer – Trading Tech

Fairygodboss; Greater London; On-site; GBP 120,000 - 190,000; Full time

Job summary

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer to design, build, and operate market gateway solutions with FPGA acceleration. You will drive the software development lifecycle with a focus on stability, latency optimization, and continuous improvement.

You will partner with hardware teams to integrate FPGA pipelines with our C++ stack, ensuring high reliability and operational excellence across global markets.

Qualifications

• Proficiency in modern C++ on Unix/Linux with strong multithreading and OO design.
• Scripting skills (Python, Perl, Shell) for automation.
• Advanced understanding of Agile methodologies, CI/CD, resiliency, and security.
• Ability to review and debug code written by others.
• Knowledge of low-level TCP/IP and network stack behavior.
• Comfort working closely with infrastructure and networking teams.
• Experience leading use of AI-assisted software development tools with validation standards.
• Strong understanding of responsible AI in engineering workflows.

Responsibilities

• Execute creative software solutions across design, development, and troubleshooting.
• Design, develop, and test reliable C++ code for trading connectivity and risk controls on Unix/Linux.
• Implement end-to-end low latency client setups, including production rollout and post-release validation.
• Automate remediation for recurring issues to improve operational stability.
• Establish and execute test strategies for latency, throughput, and resiliency.
• Lead development of market access trading and risk management modules.
• Collaborate with Application Development, Business Analysts, and Operations teams.
• Integrate FPGA pipelines with C++ software for deterministic performance.

Skills

Modern C++

Unix/Linux

Multithreading

Scripting (Python, Perl, Shell)

CI/CD

Agile methodologies

Code review

TCP/IP networking

AI-assisted tooling

Software-hardware interaction

Education

Bachelor's degree in CS/Engineering

Tools

Verilog/VHDL

PCIe

FPGA development

Linux kernel drivers

Job description

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer to design, build, and operate market gateway solutions with FPGA acceleration. You will drive the software development lifecycle with a focus on stability, latency optimization, and continuous improvement.

You will partner with hardware teams to integrate FPGA pipelines with our C++ stack, ensuring high reliability and operational excellence across global markets.