Ultra-Low Latency C++ Lead with FPGA Acceleration

Next Frontier Capital; Greater London; On-site; GBP 110,000 - 150,000; Full time

Job summary

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team in London. You will design, build, and operate market gateway solutions with FPGA acceleration, driving stability, latency optimization, and regulatory compliance.

You will partner with hardware teams to integrate FPGA pipelines with a high-performance C++ stack, affecting trading connectivity and risk management applications used globally.

Qualifications

• Proficiency in modern C++ on Unix/Linux with multithreading basics.
• Hands-on system design and production-grade development experience.
• Strong scripting (Python, Perl, Shell) for automation.
• Familiarity with Agile, CI/CD, resiliency and security.

Responsibilities

• Design and build low-latency market gateway solutions with FPGA acceleration.
• Lead software development lifecycle focusing on stability and latency.
• Integrate FPGA pipelines with C++ for deterministic performance.
• Develop automated test strategies for latency and throughput.
• Collaborate with infrastructure, networking, and operations teams.
• Advocate AI-assisted engineering practices with validated outputs.

Skills

Modern C++

Multithreading

System design

Python scripting

CI/CD

AI-assisted tooling

Networking

FPGA interaction

Education

Bachelor's degree in Computer Science/Engineering

Tools

FPGA

Verilog

VHDL

PCIe

TCP/IP

Job description

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team in London. You will design, build, and operate market gateway solutions with FPGA acceleration, driving stability, latency optimization, and regulatory compliance.

You will partner with hardware teams to integrate FPGA pipelines with a high-performance C++ stack, affecting trading connectivity and risk management applications used globally.