Lead Software Engineering - C++

JPMorganChase; Greater London; On-site; GBP 80,000 - 120,000; Full time

Job summary

JPMorganChase is seeking an Ultra Low Latency C++ Lead Software Engineer in Greater London to drive the development of market gateway solutions with FPGA hardware acceleration. The role involves executing creative software solutions among responsibilities like code development for trading connectivity on Unix/Linux platforms.

Ideal candidates will have strong expertise in C++, multithreading, Agile methodologies, and scripting languages. This position offers opportunities for career growth and a chance to contribute to high-speed trading technology on a global scale.

Qualifications

• Proficiency in modern C++ on Unix/Linux.
• Experience in production environments.
• Ability to debug code written by others.

Responsibilities

• Design, build, and operate market gateway solutions with hardware FPGA acceleration.
• Implement end-to-end low latency client setups.
• Drive team adoption of AI-assisted engineering practices.

Skills

C++ (modern)

Multithreading

Object-oriented design

Scripting (Python, Perl, Shell)

Agile methodologies

TCP/IP knowledge

AI-assisted development

Education

Bachelor's degree in Computer Science, Engineering, Mathematics or related discipline

Job description

Join us to shape the future of electronic trading technology, where your expertise in C++ and hardware acceleration will make a global impact. You will collaborate with talented engineers to deliver market‑leading solutions that power high‑speed trading across global markets. JPMorgan Chase values creativity, technical excellence, and a passion for continuous improvement, offering opportunities for career growth, skill development, and meaningful contributions. Be part of a team that thrives on solving complex challenges and advancing industry standards.

As an Ultra Low Latency C++ Lead Software Engineer in the Electronic Trading Technology team, you will design, build, and operate market gateway solutions with hardware FPGA acceleration. You will drive the software development lifecycle, focusing on stability, latency optimization, and continuous improvement, and partner with hardware engineering teams to integrate FPGA pipelines with the C++ software stack, ensuring high reliability and operational excellence.

Job Responsibilities

• Execute creative software solutions across design, development, and troubleshooting.
• Design, develop, and test reliable, high‑quality C++ code for trading connectivity and risk controls on Unix/Linux platforms.
• Implement end‑to‑end low latency client setups, including production rollout and post‑release validation.
• Automate remediation for recurring issues to improve operational stability.
• Establish and execute test strategies for latency, throughput, and resiliency.
• Drive team adoption of AI‑assisted engineering practices to improve code quality, delivery speed, and operational outcomes, establishing consistent validation standards and promoting reuse of effective patterns.
• Apply knowledge of tools within the Software Development Life Cycle toolchain, including AI‑assisted development and automation capabilities, to improve the value realized by automation.
• Lead the development of market access trading and risk management modules.
• Participate across the software development lifecycle of electronic trading services.
• Collaborate with Application Development, Business Analysts, and Operations teams.
• Integrate FPGA pipelines with C++ software for deterministic performance.

Required Qualifications, Capabilities, And Skills

• Proficiency in modern C++ on Unix/Linux with strong multithreading and object‑oriented design fundamentals.
• Hands‑on experience in system design, application development, testing, and operational stability in production environments.
• Scripting skills (Python, Perl, Shell) for automating development, testing, and operational tasks.
• Advanced understanding of Agile methodologies, including CI/CD, resiliency, and security.
• Ability to review and debug code written by others.
• Knowledge of low‑level TCP/IP and network stack behavior.
• Comfort working closely with infrastructure and networking teams.
• Demonstrated experience leading effective use of approved AI‑assisted software development tools and setting team expectations for validating AI outputs for correctness, performance, and security.
• Strong understanding of responsible AI use in engineering workflows, including data sensitivity considerations, secure handling of inputs/outputs, and adherence to resiliency and security expectations; experience coaching engineers on safe, compliant adoption within delivery practices.
• Bachelor's degree in Computer Science, Engineering, Mathematics, or related discipline.
• Excellent understanding of software‑hardware interaction.

Preferred Qualifications, Capabilities, And Skills

• Experience in low‑latency design and development using C/C++, including DMA, exchange connectivity, and pre‑trade risk systems.
• Exposure to FPGA development for financial industry applications, including embedded software and kernel driver development for FPGAs and related systems.
• Proficiency with PCI Express, TCP/IP sockets, L1/L3 switches, and integrating C++, Verilog, and VHDL solutions in Linux environments.
• Experience implementing and certifying exchange connectivity using FIX, SBE, and native binary protocols, focusing on low latency order entry and creating/automating test strategies for functional and non‑functional requirements in production‑like environments.

Equal Employment Opportunity

J.P. Morgan is an equal opportunity employer and places a high value on diversity and inclusion. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants' and employees' religious practices and beliefs, as well as mental health or physical disability needs.