System-on-Chip Design Engineer

JR United Kingdom; United Kingdom; Remote; GBP 60,000 - 100,000; Full time

Job summary

An established industry player is seeking talented engineers for a major digital transformation project in the semi-conductor sector. This exciting opportunity involves working on micro-architecture development, IP integration, and RTL coding using advanced tools and methodologies. The role offers flexibility with remote work options and requires candidates to have extensive experience in system design and integration. Join a dynamic team that values innovation and collaboration, and contribute to cutting-edge projects that shape the future of technology.

Qualifications

• 10+ years of experience in micro-architecture development.
• Experience in IP integration and RTL coding.

Responsibilities

• Develop and review micro-architecture based on customer specifications.
• Manage IP configuration and perform RTL coding.

Skills

RTL coding in System Verilog

Synthesis using Design Compiler/Fusion Compiler

RTL/gate-level debugging experience using tools such as Verdi

Job description

The provided job description contains valuable information but requires improved formatting for better readability and clarity. Additionally, some content is redundant or poorly structured, which can be streamlined to enhance understanding.

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Job Description

We are currently working with HCL on a major Digital Transformation project for a large Semi-Conductor firm based across the UK/Europe. Offices are located in Sophia Antipolis, France, and in Cambridge, UK.

Candidates should be able to travel to customer offices periodically for face-to-face interactions.

We have multiple positions open, including the primary role described below:

Common Information

• Customer: HCL for an International Semi-Conductor Client
• Duration: 15th May 2025 to 31st August 2026
• Location: Remote in Sweden or UK
• Travel Reimbursed by Client

Primary Role

Job Title: [Specify Job Title]

Responsibilities:

• Micro-architecture development and reviews based on customer specifications
• IP configuration management and rendering as per specifications
• RTL coding and design reviews
• IP integration at SS/SOC level as defined by microarchitecture
• Implement power intent using customer’s flow
• Trial synthesis, constraints updates, and logical equivalency checking (LEC)

Required Skills & Knowledge:

• RTL coding in System Verilog
• Synthesis using Design Compiler/Fusion Compiler
• RTL/gate-level debugging experience using tools such as Verdi

Additional Positions

Please indicate your preferred role among the following:

• PCIE Subsystem/SOC Integration Lead Engineer
• Experience: 10+ years
• Number of Positions: 1
• Note: Experience in PCIE IP integration required.

• Other Roles (5-10 years experience):
• Number of Positions: 2
• Note: Experience in PCIE IP integration required.

• EMMC/SDIO Subsystem/SOC Integration Lead Engineer
• Experience: 10+ years
• Number of Positions: 1
• Note: Experience in EMMC/SDIO IP integration required.

If you are interested or know someone who might be, please reach out to arrange a time to speak.