Space Avionics FPGA Engineer (RTL & Testing)

EVONA; Greater London; On-site; GBP 70,000 - 120,000; Full time

Job summary

EVONA is seeking an avionics FPGA engineer to lead RTL design and verification across the full development lifecycle for space systems. The role involves hands-on work from RTL design and simulation to hardware testing and flight readiness.

Ideal candidates will have SystemVerilog/Verilog experience, proficiency in clock-domain crossings, timing analysis, and timing closure, plus SerDes and memory interfaces.

Qualifications

• Experience with SystemVerilog and Verilog for RTL design and verification.
• Strong knowledge of clock domain crossings, static timing analysis, and timing closure.
• Experience with SerDes, memory interfaces, and high-speed I/O.
• Familiarity with Python and TCL scripting.

Responsibilities

• Hands-on role covering the full development lifecycle from RTL design and simulation through hardware testing.
• Support flight readiness and hardware validation activities.
• Develop and debug FPGA designs, interfaces, and test benches.
• Collaborate across engineering teams to ensure robust space-grade electronics.

Skills

SystemVerilog

Verilog

RTL design

RTL verification

Clock domain crossings

Static timing analysis

Timing closure

SerDes interfaces

Memory interfaces

Oscilloscopes

Logic analyzers

Python scripting

TCL scripting

Tools

Oscilloscopes

Logic analyzers

DDR memory

Microchip FPGAs

SoC design

Space-rated electronics

Job description

EVONA is seeking an avionics FPGA engineer to lead RTL design and verification across the full development lifecycle for space systems. The role involves hands-on work from RTL design and simulation to hardware testing and flight readiness.

Ideal candidates will have SystemVerilog/Verilog experience, proficiency in clock-domain crossings, timing analysis, and timing closure, plus SerDes and memory interfaces.