Autonomous Space Avionics FPGA Engineer

Lodestar; Greater London; On-site; GBP 30,000 - 75,000; Full time

Benefits offered by this job

Equity incentives

Unlimited PTO

Medical coverage

Pension

Dynamic multidisciplinary team

Job summary

Lodestar is hiring an Avionics FPGA Engineer to join our multidisciplinary team building next‑gen space systems. You will design, implement, and validate avionics architectures for autonomous platforms, from concept to on‑orbit readiness, with hands-on work across the entire lifecycle.

You will develop RTL in SystemVerilog/Verilog for FPGA targets, integrate SerDes and memory interfaces, and support testing, verification, and design reviews in a collaborative, space‑focused environment.

Qualifications

• BEng or MEng in Electrical Engineering or equivalent experience.
• Proficiency in SystemVerilog/Verilog and RTL design principles.
• Hands-on FPGA experience with at least one family.
• Familiarity with SPI, I2C, UART and digital interfaces.
• Experience with simulation and formal verification.

Responsibilities

• Design, develop, and verify RTL in SystemVerilog/Verilog for FPGA/SoC targets.
• Bring up SerDes and memory interfaces; develop testbenches.
• Perform hardware debugging and system-level testing with lab tools.
• Collaborate with systems avionics software/hardware teams for flight integration.
• Contribute to design docs, test plans, and qualification activities.

Skills

RTL design

SystemVerilog

Verilog

Python scripting

Debugging

Education

BEng/MEng in Electrical Engineering

Tools

FPGA family

SerDes interfaces

Memory interfaces

Oscilloscopes

Logic analyzers

Power supplies

PCB design (high-speed)

Lab instrumentation

Clock domain crossings

Timing analysis

Job description

Lodestar is hiring an Avionics FPGA Engineer to join our multidisciplinary team building next‑gen space systems. You will design, implement, and validate avionics architectures for autonomous platforms, from concept to on‑orbit readiness, with hands-on work across the entire lifecycle.

You will develop RTL in SystemVerilog/Verilog for FPGA targets, integrate SerDes and memory interfaces, and support testing, verification, and design reviews in a collaborative, space‑focused environment.