Senior FPGA RTL Engineer for Space Hardware (Hybrid, Equity)

American Society of Civil Engineers; Eastleigh; Hybrid; GBP 70,000 - 90,000; Full time

Benefits offered by this job

Bonus

Equity

Private Medical

Job summary

American Society of Civil Engineers in Southampton is seeking a Senior FPGA / RTL Design Engineer to build space-grade signal processing hardware for high‑throughput, real-time DSP tasks. The role is hybrid with 2 days onsite in Southampton and involves translating algorithms into efficient hardware architectures and RTL implementations.

You will work across the full development lifecycle, performing RTL design, timing closure, FPGA validation and system integration alongside Algorithm, Systems

Qualifications

• Hands-on RTL design and implementation of complex IP for FPGA and ASIC.
• Experience translating algorithms into hardware architectures and RTL implementations.
• Collaboration across Algorithm, Systems, and Verification Engineers.

Responsibilities

• Design RTL for FPGA/ASIC and deliver high-throughput DSP hardware.
• Perform timing closure, synthesis, and hardware optimisation.
• Validate FPGA and integrate with system hardware.

Skills

FPGA RTL development

Verilog SystemVerilog

Timing closure

HDL optimization

Job description

American Society of Civil Engineers in Southampton is seeking a Senior FPGA / RTL Design Engineer to build space-grade signal processing hardware for high‑throughput, real-time DSP tasks. The role is hybrid with 2 days onsite in Southampton and involves translating algorithms into efficient hardware architectures and RTL implementations.

You will work across the full development lifecycle, performing RTL design, timing closure, FPGA validation and system integration alongside Algorithm, Systems