SoC Physical Verification Lead - Tapeout Signoff

Deel; United Kingdom; Remote; GBP 90,000 - 130,000; Full time

Job summary

Deel is seeking an experienced SoC Physical Verification Engineer in the United Kingdom to lead full-chip and hierarchical signoff, including DRC, LVS, ERC, PERC, and DFM. You will work with PD, CAD, RTL, and EDA vendors to ensure tapeout-ready silicon and robust reliability across next-generation designs.

The role requires hands-on leadership, strong debugging, and scripting skills, with experience in advanced nodes and memory-centric SoCs.

Qualifications

• Experience in full-chip or block-level physical verification for advanced-node SoCs, memory, or heterogeneous integration designs.
• Strong expertise in DRC, LVS, ERC, PERC, DFM, Antenna, Reliability Verification, and Physical Verification Signoff Methodologies.
• Experience in nodes such as 22nm, 16nm, 7nm, 5nm, and below.
• Understanding RTL-to-GDSII flows and physical design impacts on verification closure.
• Strong debugging, analysis, and cross-functional collaboration skills.
• Familiarity with AI-assisted development and verification workflows.
• Experience with DRAM, Memory-Centric SoCs, Chiplets, 2.5D/3D ICs, and CPU/GPU designs.
• MS/PhD in EE/CE or related field; scripting in Python/Tcl/Perl.

Responsibilities

• Own and drive full-chip and hierarchical/signoff verification for advanced-node designs.
• Debug, customize, and deploy foundry-qualified rule decks and manage waivers.
• Perform reliability verification including ESD, latch-up, EM, and connectivity checks.
• Support parasitic RC extraction and correlate verification results with measurements.
• Develop and maintain PV automation, regression infra, and AI-assisted workflows.
• Collaborate with PD, CAD, RTL, Product Engineering, EDA vendors, and foundries.

Skills

Physical verification

Debugging

RTL-to-GDSII impact

Automation scripting

Cross-functional collaboration

AI-assisted workflows

Education

MS/PhD in EE/CE

Tools

Mentor Calibre

Synopsys IC Validator

Cadence Pegasus

ICC2/Fusion Compiler

Cadence Innovus

StarRC

Quantus

Python

Tcl

Perl

Job description

Deel is seeking an experienced SoC Physical Verification Engineer in the United Kingdom to lead full-chip and hierarchical signoff, including DRC, LVS, ERC, PERC, and DFM. You will work with PD, CAD, RTL, and EDA vendors to ensure tapeout-ready silicon and robust reliability across next-generation designs.

The role requires hands-on leadership, strong debugging, and scripting skills, with experience in advanced nodes and memory-centric SoCs.