Senior FPGA Verification Engineer - UVM Expert, Hybrid

I.T. Dev Limited; Southampton; Hybrid; GBP 55,000 - 90,000; Full time

Benefits offered by this job

IET membership fees paid

Chartered Engineer pathway

Hybrid working pattern

Profit share from day one

Job summary

ITDev in Southampton, United Kingdom seeks an experienced FPGA Verification Engineer to lead the verification of complex designs across multiple markets. You will develop verification strategies and architect scalable SystemVerilog/UVM environments, collaborating with hardware and software engineers throughout the lifecycle.

You’ll drive structured test plans, constrained-random stimulus, and coverage with a focus on high-quality verification across diverse projects.

Qualifications

• Experience verifying FPGA designs in commercial settings.
• Strong SystemVerilog and UVM expertise.
• Ability to architect reusable verification environments.
• Deep understanding of constrained-random verification and functional coverage closure.
• Experience creating verification strategies and structured test plans.
• Proficient debugging, test execution automation and fault investigation.

Responsibilities

• Develop comprehensive UVM-based verification strategies and test plans for complex FPGA designs.
• Architect and implement reusable SystemVerilog/UVM testbenches.
• Create structured test cases, constrained-random stimulus, scoreboards, assertions and coverage models.
• Define and drive metric-based verification and coverage closure.
• Run functional, system-level and regression testing.
• Analyse results, debug failures and collaborate with design engineers to fix defects.
• Develop scripts and automation frameworks for test execution and results analysis.

Skills

SystemVerilog

UVM

Verification environments

Constrained-random

Functional coverage

Test plans

Python scripting

Git

Subversion

Debugging

Documentation

Education

Electronic Engineering degree

Tools

Git

Subversion

Python

Tcl

Bash

Job description

ITDev in Southampton, United Kingdom seeks an experienced FPGA Verification Engineer to lead the verification of complex designs across multiple markets. You will develop verification strategies and architect scalable SystemVerilog/UVM environments, collaborating with hardware and software engineers throughout the lifecycle.

You’ll drive structured test plans, constrained-random stimulus, and coverage with a focus on high-quality verification across diverse projects.