Graduate Verification Engineer – Hybrid, Growth & Equity

Riverlane; Cambridge; Hybrid; GBP 37,000 - 40,000; Full time

Benefits offered by this job

Annual bonus

Private medical insurance

Life insurance

Contributory pension

Equity

Job summary

Riverlane, based in Cambridge, is hiring a Graduate Verification Engineer to join the hardware and embedded software team. You will own verification across the stack and contribute to high‑performance, trusted systems in a hybrid work environment.

No background in quantum computing is required at entry; you will learn as you go. You will develop verification plans for Quantum Error Correction blocks, build testbenches with SystemVerilog and UVM, run simulations, and collaborate with design teams

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related discipline
• Understanding of Digital Logic Design
• Some familiarity with HDL languages (Verilog, SystemVerilog) and simulation tools
• Good communication and problem-solving skills

Responsibilities

• Help with developing and executing verification plans for hardware blocks in Quantum Error Correction Systems
• Learn and support the creation of testbenches using SystemVerilog and UVM
• Run simulations and perform debugging to resolve issues in collaboration with the design team
• Collaborate with multi-disciplinary teams to understand specifications and define verification strategies for Quantum Error Correction systems
• Learn and apply best practices in verification to make methodology improvements

Skills

Electrical Engineering or Computer Sci

Digital Logic Design

Verilog/SystemVerilog

Communication skills

Problem-solving

Education

Bachelor’s or Master’s degree

Tools

SystemVerilog

UVM

Job description

Riverlane, based in Cambridge, is hiring a Graduate Verification Engineer to join the hardware and embedded software team. You will own verification across the stack and contribute to high‑performance, trusted systems in a hybrid work environment.

No background in quantum computing is required at entry; you will learn as you go. You will develop verification plans for Quantum Error Correction blocks, build testbenches with SystemVerilog and UVM, run simulations, and collaborate with design teams