Senior FPGA Verification Engineer

I.T. Dev Limited; Southampton; Hybrid; GBP 55,000 - 90,000; Full time

Benefits offered by this job

IET membership fees paid

Chartered Engineer pathway

Hybrid working pattern

Profit share from day one

Job summary

ITDev in Southampton, United Kingdom seeks an experienced FPGA Verification Engineer to lead the verification of complex designs across multiple markets. You will develop verification strategies and architect scalable SystemVerilog/UVM environments, collaborating with hardware and software engineers throughout the lifecycle.

You’ll drive structured test plans, constrained-random stimulus, and coverage with a focus on high-quality verification across diverse projects.

Qualifications

• Experience verifying FPGA designs in commercial settings.
• Strong SystemVerilog and UVM expertise.
• Ability to architect reusable verification environments.
• Deep understanding of constrained-random verification and functional coverage closure.
• Experience creating verification strategies and structured test plans.
• Proficient debugging, test execution automation and fault investigation.

Responsibilities

• Develop comprehensive UVM-based verification strategies and test plans for complex FPGA designs.
• Architect and implement reusable SystemVerilog/UVM testbenches.
• Create structured test cases, constrained-random stimulus, scoreboards, assertions and coverage models.
• Define and drive metric-based verification and coverage closure.
• Run functional, system-level and regression testing.
• Analyse results, debug failures and collaborate with design engineers to fix defects.
• Develop scripts and automation frameworks for test execution and results analysis.

Skills

SystemVerilog

UVM

Verification environments

Constrained-random

Functional coverage

Test plans

Python scripting

Git

Subversion

Debugging

Documentation

Education

Electronic Engineering degree

Tools

Git

Subversion

Python

Tcl

Bash

Job description

Southampton, United Kingdom | Posted on 29/10/2026

Apply your UVM expertise to multiple products, markets, and engineering problems.

At ITDev , you’ll take a leading role in verifying complex FPGA designs across broadcast, communications, aerospace, and other advanced engineering markets.

You’ll develop verification strategies and architect reusable SystemVerilog /UVM environments, working alongside experienced FPGA, electronics and software engineers throughout the development lifecycle.

Most of our work involves developing new products and features rather than supporting legacy systems. One project might involve high-performance video processing; another could take you into communications, aerospace or a completely new application area.

As one of our Electronics Engineers said:

“One of the attractors to me about ITDev is that there is no end to the kind of projects you can work on.”

This is an opportunity to deepen your verification expertise without becoming disconnected from the wider engineering challenge. You’ll work closely with the people designing the systems you verify, contribute to technical decisions and help shape how verification is approached across different projects.

Your professional development won’t be something you’re expected to fit around project delivery. You’ll have a personal development plan, your own mentor and dedicated time away from projects each week to work towards your development objectives.

• We’ll provide relevant training, pay your IET membership fees and support you if you want to work towards becoming a Chartered Engineer.

• You’ll also have the flexibility to work on a hybrid basis, be eligible for an uncapped annual profit share from your first day, and the support of a close-knit engineering team where people are encouraged to build long-term careers.

Our approach has been recognised by the South Coast Tech Awards: ITDev won Tech Employer of the Year in 2019, was a finalist in 2023 and has been nominated for the award again in 2026.

The role

You’ll take responsibility for the architecture and implementation of advanced SystemVerilog /UVM environments used to verify the functionality, performance and reliability of FPGA designs.

You’ll be involved in:

• Developing comprehensive UVM-based verification strategies and test plans for complex FPGA designs.
• Architecting and implementing reusable, maintainable SystemVerilog /UVM testbenches.
• Creating structured test cases, constrained-random stimulus, scoreboards, assertions and coverage models.
• Defining and driving metric-based verification and functional coverage closure.
• Running functional, system-level and regression testing.
• Analysing test results, debugging failures and working with design engineers to resolve defects.
• Developing scripts and automation frameworks for test execution, results analysis and reporting.
• Producing clear documentation covering verification architecture, requirements, test plans and results.
• Contributing to design, code and verification reviews.
• Communicating verification progress, risks and outcomes to colleagues, clients and other stakeholders.
• Applying the quality, assurance and documentation standards required across different engineering markets.
• Helping less-experienced engineers develop their understanding of advanced verification techniques.

The balance of hands-on implementation, technical leadership and stakeholder involvement will depend on the requirements of each project.

Who we’re looking for

You’re an experienced FPGA Verification Engineer with strong SystemVerilog and UVM expertise.

You know that effective verification involves more than writing tests and running regressions. You can understand a design and its requirements, identify where risk lies, decide how best to verify it and build an environment that gives the wider team confidence in the result.

You’ll need to be comfortable moving between projects and application areas. The underlying verification principles may be consistent, but the systems, risks, standards and technical challenges will change.

You’ll also be someone who communicates clearly, works collaboratively with design engineers and can explain verification decisions and results to people with different levels of technical knowledge.

Essential skills and experience

• Commercial experience verifying FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Experience architecting reusable and maintainable verification environments.
• A strong understanding of constrained-random verification, metric-driven verification and functional coverage closure.
• Experience developing verification strategies, requirements and structured test plans.
• Strong simulation, debugging and fault-investigation skills.
• The ability to analyse failures and work with design engineers to identify their underlying causes.
• Experience automating test execution using Python, Tcl , Bash or a similar scripting language.
• Experience using Git, Subversion or another revision-control system.
• The ability to produce clear technical documentation covering verification architecture, test plans, results and coverage.
• Strong analytical problem-solving skills and a quality-focused approach.
• The ability to communicate effectively with colleagues, clients and other stakeholders.
• A degree in Electronic Engineering or a closely related subject.
• Full, unrestricted right to work in the UK (we are not looking to sponsor work visas for this role)

Desirable skills and experience

• Experience with formal property checking, model checking or equivalence checking tools such as Questa Formal.
• Experience using continuous-integration pipelines for automated FPGA verification.