Verification Team Lead

microTECH Global LTD; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Benefits offered by this job

Pension

Private medical insurance

Income protection

Critical illness cover

Life cover

25 days annual leave

8 bank holidays

Job summary

microTECH Global LTD in Cambridge, UK is seeking a Senior/Lead Verification Engineer to shape verification methodology and drive production-grade open-source silicon projects such as Ibex RISC-V and OpenTitan.

You will design and debug tests with SystemVerilog/UVM, develop coverage plans, triage regressions, and contribute to open-source collaboration with major partners.

Qualifications

• 5+ years of industry experience in design verification.
• Strong SystemVerilog and UVM expertise.
• Experience across the full verification cycle (planning to tape-out).
• Familiar with Git and code review tools (GitHub, GitLab, Gerrit).
• Knowledge of RISC-V ISA or other instruction sets.
• Familiarity with formal verification tools (e.g., JasperGold).

Responsibilities

• Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM.
• Develop test and coverage plans for new and updated designs.
• Triage and debug nightly regressions.
• Review contributions to open-source projects.
• Enhance test and CI infrastructure.
• Collaborate on academic/industry publications.
• Stay current with verification best practices and introduce improvements.

Skills

SystemVerilog

UVM

RISC-V ISA

Test automation (Python/C)

Project coordination

Tools

Git

GitHub

GitLab

Gerrit

Job description

An exciting opportunity has just opened for a Senior / Lead Verification Engineer to join a cutting-edge team in Cambridge, UK, driving innovation in next-gen semiconductor projects

Location: Cambridge, UK

Duration: Permanent

Salary: Negotiable (depending on qualifications and experience)

Our client is expanding their DV team at a key growth stage, offering a rare opportunity to join early and genuinely shape verification methodology, standards, and technical direction as the team scales.

Position Overview

The work is focused on production-grade open-source silicon, including the Ibex RISC-V CPU and OpenTitan security platform, developed in collaboration with world-leading partners such as Google. This is real silicon used as a foundation for secure and scalable compute systems.

Key Responsibilities

• Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM


• Develop test and coverage plans for new and updated designs


• Triage and debug nightly regressions


• Review contributions to open-source projects


• Enhance test and CI infrastructure


• Collaborate on academic/industry publications


• Stay current with verification best practices and introduce improvements

Candidate Requirements

• 5+ years industry experience in design verification


• Strong SystemVerilog and UVM expertise


• Experience across the full verification cycle (planning to tape-out)


• Able to provide estimates and coordinate with project managers


• Comfortable in multidisciplinary, multi-organisation teams


• Familiar with Git and code review tools (GitHub, GitLab, Gerrit)


• Programming in C and/or Python for tests and automation


• Experience with multiple hardware block types


• Knowledge of security countermeasures (fault injection, side-channel attacks)


• Experience with RISC-V ISA or other instruction sets


• Familiarity with formal verification tools (e.g., JasperGold)


• 25 days annual leave + 8 bank holidays


• Employer pension contribution


• Private medical insurance, income protection, critical illness and life cover


• Opportunities to attend industry conferences and training