Senior Ultra-Low Latency C++ Engineer (FPGA)

JPMorgan Chase & Co.; Greater London; On-site; GBP 150,000 - 230,000; Full time

Job summary

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team. You will design, build, and operate market gateway solutions with hardware FPGA acceleration, driving latency optimization and reliability across global markets.

You will lead the development of market access trading and risk management modules, collaborating with hardware teams to integrate FPGA pipelines with the C++ software stack and ensuring secure, scalable production

Qualifications

• Proficient in modern C++ on Unix/Linux with multithreading and OO design principles.
• Hands-on experience in design, development, testing, and production stability.
• Scripting in Python/Perl/Shell for automation.
• Awareness of Agile, CI/CD, resiliency and security.

Responsibilities

• Design and implement high-quality C++ code for trading connectivity and risk controls on Unix/Linux.
• Develop end-to-end low-latency client setups with production rollout and validation.
• Automate remediation for recurring issues to improve stability.
• Establish test strategies for latency, throughput, and resiliency.
• Lead adoption of AI-assisted development tools and ensure validation standards.

Skills

C++ (modern)

Unix/Linux

Multithreading

AI-assisted tooling

FPGA acceleration

Education

Bachelor's degree in Computer Science

Tools

PCI Express

Verilog/VHDL

Job description

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team. You will design, build, and operate market gateway solutions with hardware FPGA acceleration, driving latency optimization and reliability across global markets.

You will lead the development of market access trading and risk management modules, collaborating with hardware teams to integrate FPGA pipelines with the C++ software stack and ensuring secure, scalable production