Senior SerDes & PHY Systems Validation Engineer

MDA Space; Farnborough; On-site; GBP 90,000 - 115,000; Full time

Benefits offered by this job

Private healthcare

Pension plan

Life insurance

Job summary

MDA Space is seeking a Sr. Systems Validation Engineer (SerDes / Physical Layer) to join our Farnborough team. You will validate high‑speed SerDes PHY, perform link bring‑up, and tune equalization while coordinating with the Chip Validation Team Leader.

You will develop chip and system test plans, automate tests in Python, and analyze results to ensure robust silicon and system performance across data rates and environments.

Qualifications

• Bachelor's or Master's degree in Electronic/Computer Science Engineering.
• 8–13 years post‑graduate experience preferred.
• Experience testing Telecommunication or Satellite Systems.
• Experience with chip and system testing, especially analog, RF and high-speed blocks.
• Knowledge of SerDes time-domain links and related equipment (BERT, DCA).
• Proficient in automation testing (C/C++/Python).
• Strong debugging and problem-solving skills.
• Familiarity with defect tracking tools (JIRA/Confluence).

Responsibilities

• Validate high-speed SerDes PHY and perform link bring-up.
• Tune equalization and conduct PVT testing across data rates.
• Develop test plans for chip and system tests with dev and test teams.
• Create test automation in Python for chip and system tests.
• Investigate test failures and drive corrective actions with development teams.
• Support test management tools and CI methodologies.
• Analyze data and post-process results to improve product quality.

Skills

SerDes

Python

C/C++

Lab automation

Debugging

Education

Bachelor/Master in Electronic/Computer Science Engineering

Tools

JIRA

Confluence

Python scripting

Job description

MDA Space is seeking a Sr. Systems Validation Engineer (SerDes / Physical Layer) to join our Farnborough team. You will validate high‑speed SerDes PHY, perform link bring‑up, and tune equalization while coordinating with the Chip Validation Team Leader.

You will develop chip and system test plans, automate tests in Python, and analyze results to ensure robust silicon and system performance across data rates and environments.