Senior DDR Validation & FPGA Engineer – Space Systems

MDA; Farnborough; On-site; GBP 75,000 - 110,000; Full time

Job summary

MDA Space in Farnborough is seeking an experienced engineer to drive DDR validation, FPGA development and system bring-up for high-speed modem platforms.

You will collaborate with RTL, memory controller, PHY and software teams, perform margin/eye analyses, develop automated validation scripts, and ensure production readiness through rigorous stress testing. A strong background in high-speed digital systems is essential.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 8-15 years total post-graduation experience sought.
• 5–12+ years in DDR validation, FPGA development, or high-speed digital systems.
• Knowledge of DDR3/DDR4 and JEDEC standards.
• Experience with modem or wireless SoCs (4G/5G).

Responsibilities

• Validate DDR3/DDR4 interfaces on modem platforms.
• Develop DDR validation plans covering functionality, timing, electrical, and performance.
• Perform DDR margin analysis: timing, voltage, frequency, temperature.
• Debug memory training failures, calibration issues, and initialization sequences.
• Perform read/write eye analysis and BER measurements.
• Analyze DDR performance bottlenecks using hardware and software tools.
• Develop FPGA-based prototypes and bring up FPGA platforms.
• Support hardware/software co-validation using FPGA platforms.

Skills

DDR validation

FPGA development

System bring-up

Python

C/C++

Debugging skills

Strong communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog

Git

Regression frameworks

BERT

TDR

Job description

MDA Space in Farnborough is seeking an experienced engineer to drive DDR validation, FPGA development and system bring-up for high-speed modem platforms.

You will collaborate with RTL, memory controller, PHY and software teams, perform margin/eye analyses, develop automated validation scripts, and ensure production readiness through rigorous stress testing. A strong background in high-speed digital systems is essential.