Senior Process Integration Engineer - Semiconductors

Nexperia

Manchester

Hybrid

GBP 90,000 - 120,000

Full time

14 days+

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Benefits offered by this job

Hybrid working policy
Generous leave / 33 days
Pension scheme
Relocation assistance

Job summary

Nexperia in Manchester is seeking a Principal Process Integration Engineer to lead process development for 200mm and 300mm MOSFET platforms, collaborating with third‑party fabs and internal teams to optimise small signal device fabrication.

The role requires a Master’s degree in semiconductor science, 5+ years’ wafer fab experience, and deep trenches MOS knowledge, with strong DOE planning and communication skills; travel up to 10% is expected, with hybrid working and a competitive rewards

Qualifications

  • Master’s degree in semiconductor field is required.
  • Minimum 5 years’ experience in semiconductor fab process integration.
  • Strong knowledge of trench MOS on low/high voltage platforms (30/40/60V and 80/100V).
  • Experience with modules such as Mask, Etch, PVD, CVD, and Diffusion.

Responsibilities

  • Develop technologies for 200mm and 300mm platforms and work with fabs/vendors.
  • Lead process development or integration projects with minimal supervision.
  • Support qualification of new process and product developments (substrate and epi).
  • Plan DOEs, report results with clear conclusions, and share knowledge.

Skills

Semiconductor process integration
5+ years semiconductor fab experience
Trench MOS knowledge
Mask/Etch/CVD/PVD/Diffusion knowledge
Team player with strong communication
Willingness to travel up to 10%

Education

Master’s Degree in Semiconductor Device Physics / Semiconductor Technology / Microelectronics

Job description

Nexperia in Manchester is seeking a Principal Process Integration Engineer to lead process development for 200mm and 300mm MOSFET platforms, collaborating with third‑party fabs and internal teams to optimise small signal device fabrication.

The role requires a Master’s degree in semiconductor science, 5+ years’ wafer fab experience, and deep trenches MOS knowledge, with strong DOE planning and communication skills; travel up to 10% is expected, with hybrid working and a competitive rewards

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