Lead Full-Chip Physical Design Architect

Aion Silicon; Greater London; Hybrid; GBP 130,000 - 190,000; Full time

Job summary

Aion Silicon is seeking a Principal Physical Design Engineer to lead complete physical implementation of complex SoCs and ASICs. You will own RTL handoff to sign‑off and GDSII generation, coordinating with RTL, STA, DFT, packaging, foundry and EDA partners globally.

You will mentor engineers, drive design strategies for 7nm and below, and ensure timely tape‑outs while staying ahead with industry best practices.

Qualifications

• 10+ years of Physical Design experience with a proven track record of full‑chip delivery.
• Expertise in advanced technology nodes (7nm, 5nm and below).
• Experience delivering multiple complex SoC or ASIC tape‑outs.
• Demonstrated leadership mentoring and developing engineers.
• Strong customer engagement and stakeholder management skills.
• Excellent communication and ability to influence technical direction across teams.

Responsibilities

• Lead full‑chip physical implementation for complex SoC and ASIC designs.
• Define and drive chip‑level physical design strategies, methodologies and best practices.
• Coordinate with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve design closure.
• Mentor and coach Physical Design engineers and drive team capability development.
• Review and approve block‑level physical design deliverables before integration.
• Lead technical reviews, debug sessions and closure activities.
• Support recruitment activities and help build a world‑class team.
• Represent the company at universities, conferences and industry events to promote innovation.

Education

Master's or PhD in a relevant engineering discipline

Tools

ICC2

Fusion Compiler

PrimeTime

StarRC

ICV

Innovus

Tempus

Voltus

Genus

Calibre

Job description

Aion Silicon is seeking a Principal Physical Design Engineer to lead complete physical implementation of complex SoCs and ASICs. You will own RTL handoff to sign‑off and GDSII generation, coordinating with RTL, STA, DFT, packaging, foundry and EDA partners globally.

You will mentor engineers, drive design strategies for 7nm and below, and ensure timely tape‑outs while staying ahead with industry best practices.