Physical Design Engineer

Platform Recruitment; West of England; On-site; GBP 230,000 - 270,000; Full time

Benefits offered by this job

Equity

Job summary

Platform Recruitment is assisting a rapidly growing semiconductor company in the Bristol area to recruit a Senior/Staff Physical Design Engineer. You will lead physical design from architecture through sign-off, collaborating with analogue, digital and DFT engineers to tackle complex high-frequency challenges.

Key responsibilities include floorplanning, routing, clocking networks and power-grid design, with tape-out support on advanced-node processes.

Qualifications

• Minimum seven years' ASIC or SoC physical design experience.
• Experience with high-frequency, high-performance digital implementation.
• Experience across floorplanning, placement and routing, CTS, STA and sign-off.

Responsibilities

• Architecting and implementing high-performance digital control solutions.
• Floorplanning, placement, routing and timing closure.
• Developing low-power, low-skew clock-distribution networks.
• Designing power grids around complex analogue floorplans.
• Supporting multi-voltage-domain design flows.
• Performing timing analysis across analogue and digital interfaces.
• Achieving DRC, LVS and ERC closure on advanced-node processes.
• Customising and automating physical-design flows using Python and Tcl.
• Supporting DFT implementation and successful tape-out.

Skills

ASIC/SoC physical design

Digital high-frequency implementation

Floorplanning

Place & Route

CTS

STA

Sign-off

Python scripting

Tcl scripting

Digital-Analogue integration

Tools

EDA flow automation tools

Job description

Senior / Staff Physical Design Engineer

Location: Bristol Area

Salary: Circa £250,000 + Equity

Working Arrangement: On-site

Employment Type: Permanent

I’m recruiting on behalf of a rapidly growing semiconductor company developing next-generation accelerator technology for high-performance AI computing.

They are seeking a Senior or Staff Physical Design Engineer to lead the implementation of digital control logic within a tightly integrated mixed-signal and analogue subsystem. This is an opportunity to solve complex physical-design challenges involving advanced process nodes, high-frequency circuits and custom analogue/RF integration.

The Role

You will take ownership of physical design from architecture through to sign-off, working closely with analogue, digital and DFT engineers.

Key responsibilities will include:

• Architecting and implementing high-performance digital control solutions.
• Floorplanning, placement, routing and timing closure.
• Developing low-power, low-skew clock-distribution networks.
• Designing power grids around complex analogue floorplans.
• Supporting multi-voltage-domain design flows.
• Performing timing analysis across analogue and digital interfaces.
• Achieving DRC, LVS and ERC closure on advanced-node processes.
• Customising and automating physical-design flows using Python and Tcl.
• Supporting DFT implementation and successful tape-out.

Essential Experience

• At least seven years’ experience in ASIC or SoC physical design.
• Strong knowledge of high-frequency, high-performance digital implementation.
• Experience across floorplanning, place and route, CTS, STA and sign-off.
• Proven work with advanced semiconductor process nodes.
• Python and Tcl scripting for EDA flow automation.
• Experience integrating digital logic with analogue, RF or mixed-signal circuitry.
• Strong communication and cross-functional collaboration skills.

Experience with sub-7nm tape-outs, PCIe, SerDes, PHY integration, ESD requirements or customised DFT flows would be highly advantageous.

The successful engineer will receive a circa £250,000 salary, meaningful equity and the opportunity to influence the architecture of a genuinely cutting-edge semiconductor platform.