Senior IP Design Engineer - Remote FPGA/SoC & 100GbE/PCIe

DCV Technologies; Remote; GBP 125,000 - 150,000; Full time

Job summary

A leading technology company is seeking a Senior IP Design Engineer for a remote contract role in the UK. The successful candidate will design high-performance digital IP targeting FPGA and Adaptive SoC platforms. Responsibilities include implementing SystemVerilog RTL and optimising high-speed digital interfaces such as 100Gb Ethernet and PCIe Gen5. This position requires strong experience with Vivado, Python, and CI/CD workflows, and is available for immediate start.

Qualifications

• Strong SystemVerilog RTL design experience required.
• Experience with FPGA/Adaptive SoC design flow: synthesis, P&R, timing closure.
• Knowledge of high-speed digital interfaces like 100GbE and PCIe Gen5.

Responsibilities

• Design high-performance IP using SystemVerilog RTL.
• Deliver synthesis-ready RTL meeting timing and integration requirements.
• Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks.
• Drive timing closure using Vivado toolchains.
• Develop automation using Python/Tcl scripting.

Skills

SystemVerilog RTL design experience

FPGA/Adaptive SoC design flow

High-speed digital interfaces: 100GbE / PCIe Gen5 / AXI

Vivado / Vitis expertise

Python/Tcl, Git, CI/CD experience

Job description

A leading technology company is seeking a Senior IP Design Engineer for a remote contract role in the UK. The successful candidate will design high-performance digital IP targeting FPGA and Adaptive SoC platforms. Responsibilities include implementing SystemVerilog RTL and optimising high-speed digital interfaces such as 100Gb Ethernet and PCIe Gen5. This position requires strong experience with Vivado, Python, and CI/CD workflows, and is available for immediate start.