Senior IP Design Engineer (FPGA / Adaptive SoC)

N Consulting Limited; Belfast; Remote; GBP 32,081 - 40,101; Full time

Job summary

A technology consulting firm is looking for a highly skilled Senior IP Design Engineer (FPGA / Adaptive SoC). This is a fully remote opportunity for candidates in the UK or Eastern Europe. You will design and develop high-performance IP cores while collaborating with various teams. Requirements include strong experience in SystemVerilog RTL design and familiarity with FPGA design flows. The role offers a contract duration of 6 months with a daily rate between €200 - €250.

Qualifications

• Strong experience in SystemVerilog RTL design.
• Proven expertise with 100Gb Ethernet, PCIe Gen5, and AMBA/AXI protocols.
• Hands-on experience with synthesis, place & route, and timing closure.

Responsibilities

• Design and implement high-performance, synthesis-ready IP cores using SystemVerilog RTL.
• Develop IP for high-speed interfaces, including 100Gb Ethernet.
• Drive FPGA/Adaptive SoC design flow, including synthesis and timing closure.

Skills

SystemVerilog RTL design

High-speed interfaces (100Gb Ethernet, PCIe Gen5, AMBA/AXI)

Performance optimization

Python scripting

Tcl scripting

Git and CI/CD environments

Tools

Vivado/Vitis

Job description

LocationUK/Belfast/ any Eastern European Countries, United Kingdom# Senior IP Design Engineer (FPGA / Adaptive SoC) at N Consulting LtdLocationUK/Belfast/ any Eastern European Countries, United KingdomSalary€200 - €250 /dayJob TypeContractDate PostedMarch 4th, 2026Apply NowSenior IP Design Engineer (FPGA / Adaptive SoC) Location: 100% Remote (UK, Belfast, or Eastern Europe) Type: 6 months ContractOverview We are seeking a highly skilled Senior IP Design Engineer to design and develop high-performance IP cores targeting FPGA and Adaptive SoC technologies. This is a fully remote opportunity open to candidates based in the UK (including Belfast) and Eastern Europe. The ideal candidate will have deep expertise in SystemVerilog RTL design and a strong understanding of FPGA design flows, including place & route and timing closure.Key Responsibilities Design and implement high-performance, synthesis-ready IP cores using SystemVerilog RTL Develop IP for high-speed interfaces such as 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Drive FPGA/Adaptive SoC design flow including synthesis, place & route (P&R), and timing closure Optimize designs for performance, area, and power Work closely with verification, system, and software teams for seamless IP integration Develop automation scripts using Python and Tcl Maintain high-quality code using Git and support CI/CD workflows Support integration, bring-up, and debugging activities as requiredRequired Skills & Experience Strong experience in SystemVerilog RTL design Proven expertise with: 100Gb Ethernet PCIe Gen5 AMBA/AXI protocols Deep understanding of FPGA/Adaptive SoC architecture and design flows Hands-on experience with synthesis, place & route, and timing closure Strong working knowledge of Vivado/Vitis Proficiency in Python and Tcl scripting Experience with Git and CI/CD environments Ability to work independently in a remote, distributed teamPreferred Qualifications Experience with high-speed data path design Familiarity with performance optimization techniques for large FPGA designs Exposure to lab bring-up and hardware debugging Experience mentoring junior engineers