Senior FGPA Engineer

Platform Recruitment; Cambridge; On-site; GBP 70,000 - 100,000; Full time

Job summary

Platform Recruitment is seeking a Senior FPGA Engineer in Cambridge to oversee RTL design on ultra-low-latency platforms. You will architect RTL on high-end FPGAs, drive verification environments, and collaborate with firmware, software and infrastructure teams to optimise full-stack performance.

Required 7+ years FPGA/RTL experience, SystemVerilog, and hands-on with Vivado or Quartus. Familiarity with AXI/PCIe/Ethernet interfaces is preferred.

Qualifications

• 7+ years FPGA/RTL design experience in timing-critical systems.
• Strong background in SystemVerilog, synthesis, timing closure and verification.
• Hands-on with Vivado/Quartus or equivalent toolchains.
• Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.

Responsibilities

• Architect RTL designs on high-end FPGAs (Xilinx / Intel).
• Perform simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems.
• Lead the definition of micro-architectures and verification environments.
• Drive technical excellence through mentorship and code reviews.
• Collaborate with firmware, software and infrastructure teams to optimise performance.

Skills

SystemVerilog

FPGA RTL design

C/C++ or Python

High-speed interfaces

Tools

Vivado

Quartus

Job description

Senior FPGA Engineer | £(Apply online only)k | Cambridge

This is an opportunity to join a global team developing ultra-low latency technology.

You will oversee all aspects of FPGA system design, driving advancements to ensure my client maintains its technological advantage by building the next generation of infrastructure.

Responsibilities as a Senior FPGA Engineer:

• Architecting and implementing RTL designs on high-end FPGAs (Xilinx / Intel).
• Performing simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems.
• Leading the definition of micro-architectures and verification environments.
• Driving technical excellence across the FPGA team through mentorship and code reviews.
• Collaborating with firmware, software and infrastructure teams to optimise full-stack performance.

Requirements:

• 7+ years' FPGA / RTL design experience in timing-critical systems.
• Strong background in SystemVerilog, synthesis, timing closure and verification.
• Hands-on with Vivado / Quartus or equivalent toolchains.
• Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.

Bonus skills for a Senior FPGA Engineer:

• Exposure to high-performance computing, networking or real-time data systems.
• Knowledge of C/C++ or Python for tooling, verification or firmware collaboration.
• Appreciation for hardware-software co-design and system-level optimisation