Field-Programmable Gate Arrays Engineer

Gazelle Global; England; Remote; GBP 50,000 - 70,000; Full time

Job summary

A leading tech consultancy is seeking a Mid-Senior level engineer with strong SystemVerilog RTL capabilities for a fully remote role from the UK. You will possess confidence across 100Gb Ethernet, PCIe Gen5, and AXI while being comfortable taking designs through to timing closure. Experience with Vivado and Vitis, and proficiency in Python or TCL to streamline work is essential. Join a culture that respects engineering excellence and offers genuine technical ownership.

Responsibilities

• Genuine technical ownership in projects.
• Support high-performance IP on next generation FPGA.

Skills

SystemVerilog RTL capability

Confident across 100Gb Ethernet

Experience with Vivado

Proficient in Python or TCL

Familiar with Git and CI

Tools

Vivado

Vitis

Job description

Job Overview

I’m getting in touch because I’m supporting a client who are pushing the boundaries of high‑performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. The role is fully remote from the UK with genuine technical ownership and a culture that respects engineering excellence. If this aligns even just slightly with what you’d consider for your next move, would you be open to a brief conversation?

Technical Requirements

• Strong SystemVerilog RTL capability
• Confident across 100Gb Ethernet, PCIe Gen5, and AXI
• Comfortable taking designs through to timing closure without fuss
• Experience with Vivado and Vitis
• Proficient in Python or TCL to streamline work
• Familiar with modern development practices, Git, and CI

Employment Details

• Seniority level: Mid‑Senior level
• Employment type: Contract
• Job function: Information Technology, Consulting, and Engineering
• Industries: Staffing and Recruiting, Robotics Engineering, and Engineering Services