Senior IC PDK Engineer — Flexible Work & Share Options

Quantum; City of Westminster; On-site; GBP 90,000 - 140,000; Full time

Benefits offered by this job

Competitive salary & share options

Contributory pension

Private Medical Insurance

Life Assurance

Cycle-to-work

Flexible working

Central London Islington

Job summary

Quantum Motion is seeking an experienced IC PDK engineer to architect, implement, and maintain custom PDKs and SVRF rule decks for cryogenic CMOS and spin-qubit silicon technologies. You will integrate Cadence Virtuoso with tier-1 PDKs, develop PCells, and collaborate with IC designers and layout engineers to enable reliable physical verification.

The role requires hands-on expertise in Cadence SKILL, Calibre SVRF, LVS/DRC, and complex layout environments at deep-submicron nodes, plus strong

Qualifications

• Industry degree in Electronic Engineering, IC Layout, Computer Science, or related physical science/engineering.
• Hands-on IC PDK development and PDK enablement flow management.
• Proficiency with Cadence SKILL/ Virtuoso and Calibre SVRF for DRC/LVS.

Responsibilities

• Develop custom PDK elements from scratch: Schematic symbols, Layout SKILL PCells, and DRC/LVS decks.
• Create, qualify, and maintain Calibre SVRF rule decks for non-standard layouts and cryogenic CMOS constraints.
• Integrate tier-1 PDKs into Cadence Virtuoso with customized libraries & layer maps.
• Collaborate with IC designers and layout engineers to establish best practices for physical verification and layout automation.
• Document work for peer review and evaluate layout/enablement work of team members.

Skills

Cadence SKILL

Virtuoso PDK

Calibre SVRF

LVS/DRC debugging

Cryogenic CMOS

Education

Electronic Engineering (degree)

Tools

Cadence Virtuoso

Cadence SKILL

Siemens Calibre

Verilog-A/BSIM

Job description

Quantum Motion is seeking an experienced IC PDK engineer to architect, implement, and maintain custom PDKs and SVRF rule decks for cryogenic CMOS and spin-qubit silicon technologies. You will integrate Cadence Virtuoso with tier-1 PDKs, develop PCells, and collaborate with IC designers and layout engineers to enable reliable physical verification.

The role requires hands-on expertise in Cadence SKILL, Calibre SVRF, LVS/DRC, and complex layout environments at deep-submicron nodes, plus strong