Senior IC PDK Development Engineer

United States Digital Space LLC; Greater London; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Competitive salary

Share options scheme

Contributory pension

Private Medical Insurance

Life Assurance

Cycle-to-work

Flexible working

Central London location

Job summary

Quantum Motion, a fast-growing quantum computing startup based in London, seeks an experienced IC PDK Engineer to architect, build and maintain custom PDK components for cryogenic silicon devices. You will bridge foundry technologies with circuit design, develop SKILL PCells, Calibre SVRF rules, and integrate Cadence Virtuoso PDKs alongside layout automation.

Ideal candidates have 5+ years in IC PDK development, strong Cadence and Calibre expertise, and excellent communication to collaborate

Qualifications

• Industry degree in Electronic Engineering, IC Layout, CS or related field.
• 5+ years in IC PDK development and enablement flow.
• Proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
• Proficiency in Siemens Calibre Physical Verification tools and SVRF rule writing.
• Experience debugging DRC/LVS in analog/mixed-signal or custom digital layouts.
• Strong analytical, self-management and cross-disciplinary collaboration.

Responsibilities

• Develop custom PDK elements from scratch (Schematic symbols, PCells, DRC/LVS decks).
• Qualify and maintain Calibre SVRF rule decks for cryogenic CMOS layouts.
• Integrate Tier-1 foundry PDKs into Cadence Virtuoso with library extensions.
• Work with IC designers to establish best practices for verification and layout automation.
• Document work for peer review and mentor other team members.

Skills

Cadence SKILL PCell

Virtuoso PDK customization

SVRF Rule Writing

Analog/Mixed-Signal Layout

PDS DRC/LVS debugging

Education

Electronic Engineering

IC Layout

Computer Science

Tools

Cadence Virtuoso

Calibre SVRF

Job description

About The Role and Team

Quantum Motion is a fast-growing quantum computing start-up based in London. We are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence, and cybersecurity. We operate out of state-of-the-art cryogenic facilities in Islington and bring together an outstanding interdisciplinary team spanning quantum physics to IC design.

Our Team

Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC, and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We are backed by a world-class group of investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Science Enterprises, INKEF Capital, and Octopus Ventures.

Functions of the Role

The primary function of this position will be to architect, build, and maintain our custom process design kits (PDKs) and physical verification enablements. In this role, you will sit within the IC Design team, serving as the critical bridge between foundry technologies, custom cryogenic silicon devices, and our circuit design group. You will create custom PDK components from scratch and enable novel silicon spin-qubit and cryo-CMOS circuit design methodologies. No prior background in quantum physics is required.

• Development of custom PDK elements from scratch, including Schematic symbols, Layout SKILL PCells, and custom DRC and LVS decks.
• Development, qualification, and maintenance of custom Calibre SVRF rule decks tailored for non-standard layout constraints and cryogenic CMOS layout considerations.
• Integrate tier-1 foundry PDKs into Cadence Virtuoso, creating customized library extensions, layer maps, and device callbacks.
• Work closely with IC designers and layout engineers to establish best practices for physical verification and layout automation.
• Document own work for peer review and evaluate the layout and enablement work of other team members.

Experience – Essentials

• Industry degree qualification in Electronic Engineering, IC Layout, Computer Science, or a related physical science/engineering field.
• 5+ years of hands‑on industry experience in IC PDK Development and PDK enablement flow management.
• Demonstrated proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
• Demonstrated proficiency in Siemens Calibre Physical Verification tools and SVRF Rule writing (specifically for DRC and LVS decks).
• Proven hands‑on experience in complex DRC and LVS error debugging within analog/mixed‑signal or custom digital layout environments.
• Strong analytical and problem‑solving skills with a high level of self‑management, self‑motivation, and willingness to engage actively in peer code and layout reviews.
• Excellent verbal and written communication skills to collaborate effectively across multidisciplinary physics and IC engineering teams.

Experience – Desirable

• Demonstrated experience with advanced deep‑submicron CMOS nodes (40nm, 28nm, or below), including familiarity with layout‑dependent effects (LOD, WPE, OSE, etc.).
• Expert knowledge of the Cadence Virtuoso Design Environment and Cadence SKILL / SKILL++ programming.
• Expert knowledge of the Siemens Calibre Physical Verification Environment.
• Familiarity with MOSFET device modeling integration (e.g., BSIM, Verilog‑A) or cryogenic device enablement.
• General awareness or curiosity regarding semiconductor quantum dots or silicon spin qubit fundamentals.

Benefits

• Be part of a creative, world‑leading team
• Competitive salary and share options scheme
• Contributory pension scheme
• Private Medical Insurance
• Life Assurance
• Cycle‑to‑work Scheme
• Flexible working
• Central London location (Islington)

EEO Statement

Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment, or any other protected characteristics covered by the Equality Act 2010.

Internal Job Reference Number

HRS - 81