Senior Hardware Verification Engineer – Testbench Architect

Semiconductor Engineering; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Benefits offered by this job

Test environment support

Job summary

Semiconductor Engineering seeks a seasoned Design Verification designer to lead testbench development for complex IPs. The role emphasizes writing test sequences and building robust verification environments to ensure reliable interconnectivity across SoC, chiplet, or multi-chiplet configurations.

You will create test plans, implement UVM/SystemVerilog code, and collaborate with software and design teams on verification strategies, coverage, and failure debugging.

Qualifications

• Experience writing test plans for configurable IPs.
• Proficiency with UVM and SystemVerilog for testbench development.
• Experience verifying IPs across SoC and multi-chiplet systems.

Responsibilities

• Create test plans for configurable IPs enabling interconnectivity across components in SoC, chiplet, or multi-chiplet systems.
• Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design teams on test plans, failure debug, coverage, and related tasks.

Skills

Testbenches

UVM SystemVerilog

IP Verification

SoC Interconnectivity

Test Sequences

Job description

Semiconductor Engineering seeks a seasoned Design Verification designer to lead testbench development for complex IPs. The role emphasizes writing test sequences and building robust verification environments to ensure reliable interconnectivity across SoC, chiplet, or multi-chiplet configurations.

You will create test plans, implement UVM/SystemVerilog code, and collaborate with software and design teams on verification strategies, coverage, and failure debugging.