Senior FPGA Engineer: Real-Time Quantum Control

Quantum Computing Jobs UK; Oxford; On-site; GBP 85,000 - 110,000; Full time

Benefits offered by this job

IonQ stock options

Annual performance bonus

Generous leave

Job summary

IonQ is seeking a Staff FPGA Engineer to join the FPGA Team and design RTL modules for real-time quantum control. You will own architecture for high‑speed waveform generation and contribute to a world‑class quantum computer effort.

The role requires extensive FPGA experience, proficiency with SystemVerilog, Vivado, and verification tools, and strong scripting in Python or MATLAB. On-site in Oxford, UK, with a technology‑driven, collaborative team.

Qualifications

• Bachelor’s degree in a technical field and 10+ years hands‑on FPGA development experience.
• Experience designing, verifying, and debugging FPGA-based systems with focus on signal processing.
• Strong knowledge of DDC/DUC, DDS, and FIR/IIR filters.
• Proficiency in Python and/or MATLAB/Simulink for modelling and verification.
• Familiarity with industry verification tools (Synopsys, Cadence, ModelSim).

Responsibilities

• Design, develop, and test RTL modules for real-time control of quantum systems.
• Own and architect critical FPGA control functions for high‑speed waveform generation.
• Write test procedures and perform unit and system level testing.
• Perform logic design and verification using Vivado and associated simulators.
• Collaborate with cross‑functional teams to gather requirements and deliver results.

Skills

FPGA design

RTL development

SystemVerilog

Python/MATLAB

JTAG & logic analyzers

Education

Bachelor’s degree in Electrical Engineering, Physics, Mathematics

Tools

Vivado

ModelSim

Synopsys

Cadence

Xilinx Ultrascale+ MPSoC

MATLAB/Simulink

Job description

IonQ is seeking a Staff FPGA Engineer to join the FPGA Team and design RTL modules for real-time quantum control. You will own architecture for high‑speed waveform generation and contribute to a world‑class quantum computer effort.

The role requires extensive FPGA experience, proficiency with SystemVerilog, Vivado, and verification tools, and strong scripting in Python or MATLAB. On-site in Oxford, UK, with a technology‑driven, collaborative team.