Senior FPGA Engineer for Quantum Hardware Systems

Oxford Quantum Circuits (OQC); Reading; On-site; GBP 85,000 - 120,000; Full time

Job summary

Oxford Quantum Circuits (OQC) is seeking a Senior FPGA Engineer for the Advanced Product Development Group to build purpose-built FPGA hardware for quantum computing. The role blends deep HDL expertise with system-level thinking and cross-functional collaboration.

You will drive deterministic timing, multi-card communication, and high-speed interfaces for ADCs/DACs and RF SoC platforms while mentoring junior engineers and contributing to project planning and documentation.

Qualifications

• Proficient in SystemVerilog/VHDL and Verilog HDL for FPGA design.
• Experience achieving timing closure on high-utilization FPGA designs and writing timing constraints.
• Familiar with RF/microwave hardware interfaces and DSP concepts.

Responsibilities

• Define scalable FPGA architectures with deterministic timing, synchronization, maintainability, and multi-card communication.
• Design, implement, and verify RTL for high-performance microwave/RF applications.
• Develop interfaces and control logic for high-speed ADCs/DACs and memory systems.
• Implement real-time DSP algorithms optimized for FPGA resources and multi-clock domains.
• Support bring-up, lab integration, verification, and system-level testing.
• Collaborate with Electronics, Embedded Software, Mechanical, Cryogenic, and Deployment teams to deliver integrated systems.
• Mentor junior engineers through code reviews and best practices; contribute to planning and documentation.

Skills

System Verilog

VHDL

Verilog

Timing closure

FPGA architectures

RF/microwave knowledge

DSP for FPGA

RTL design

Education

Bachelor's degree in Engineering or related technical discipline

Tools

Quartus

MATLAB/Simulink

Oscilloscopes

Job description

Oxford Quantum Circuits (OQC) is seeking a Senior FPGA Engineer for the Advanced Product Development Group to build purpose-built FPGA hardware for quantum computing. The role blends deep HDL expertise with system-level thinking and cross-functional collaboration.

You will drive deterministic timing, multi-card communication, and high-speed interfaces for ADCs/DACs and RF SoC platforms while mentoring junior engineers and contributing to project planning and documentation.