Senior FPGA Design Engineer

American Society of Civil Engineers; Eastleigh; Hybrid; GBP 70,000 - 90,000; Full time

Benefits offered by this job

Bonus

Equity

Private Medical

Job summary

American Society of Civil Engineers in Southampton is seeking a Senior FPGA / RTL Design Engineer to build space-grade signal processing hardware for high‑throughput, real-time DSP tasks. The role is hybrid with 2 days onsite in Southampton and involves translating algorithms into efficient hardware architectures and RTL implementations.

You will work across the full development lifecycle, performing RTL design, timing closure, FPGA validation and system integration alongside Algorithm, Systems

Qualifications

• Hands-on RTL design and implementation of complex IP for FPGA and ASIC.
• Experience translating algorithms into hardware architectures and RTL implementations.
• Collaboration across Algorithm, Systems, and Verification Engineers.

Responsibilities

• Design RTL for FPGA/ASIC and deliver high-throughput DSP hardware.
• Perform timing closure, synthesis, and hardware optimisation.
• Validate FPGA and integrate with system hardware.

Skills

FPGA RTL development

Verilog SystemVerilog

Timing closure

HDL optimization

Job description

Senior FPGA / RTL Design Engineer

Build Tech That Will Orbit the Earth

Southampton (Hybrid 2 days onsite)

Circa £70,000 + Bonus + Equity + Private Medical

Satellites are getting smarter. This team is building the signal processing hardware that’s making it happen. They’re tackling one of the toughest challenges in wireless communications: putting full 5G base stations into orbit. That means designing high‑performance FPGA and ASIC hardware capable of delivering real‑time, high‑throughput digital signal processing on space‑qualified devices.

This is a hands‑on engineering role focused on RTL design and implementation of complex IP for FPGA and ASIC. You’ll work across the full development lifecycle from translating algorithms into efficient hardware architectures through to RTL implementation, timing closure, FPGA validation and system integration working alongside Algorithm, Systems and Verification Engineers.

What we’re looking for

• FPGA / RTL development using Verilog or SystemVerilog
• High‑speed, high‑throughput digital hardware or DSP implementations
• Timing closure, synthesis and hardware optimisation
• Complex FPGA or ASIC development projects

Experience with wireless communications, UVM, Python or AMBA would be advantageous, but isn’t essential.

Why join?

Because opportunities like this don’t come along very often. You’ll be solving genuinely difficult engineering problems, working with some of the UK’s leading communications engineers, and developing technology that will become part of the next generation of global 5G satellite infrastructure.

If that sounds like your kind of challenge, we’d love to hear from you.