Senior FPGA/ASIC Design Engineer for Space & 5G

Spectrum IT Recruitment; Southampton; On-site; GBP 70,000 - 95,000; Full time

Job summary

Spectrum IT Recruitment is seeking an experienced Senior Design Engineer to help develop cutting-edge communications technology for global connectivity. The role focuses on next‑generation 5G non‑terrestrial networks and satellite‑based systems, taking designs from architecture to validation on space‑qualified hardware platforms.

You will design high‑performance RTL for FPGA/ASIC targets, optimise for throughput and power, and collaborate across multiple engineering teams within an Agile

Qualifications

• RTL design experience with Verilog/SystemVerilog.
• Experience delivering complex FPGA/ASIC designs.
• Knowledge of synthesis, timing analysis and power optimisation.
• Proficiency with industry-standard EDA tools.

Responsibilities

• Translate system and algorithm requirements into RTL micro-architectures.
• Design RTL using Verilog/SystemVerilog for FPGA and ASIC targets.
• Create testbenches and support functional verification.
• Deploy and validate designs on FPGA development platforms.
• Optimise designs for performance, timing, power and resources.
• Produce high‑quality technical documentation.
• Collaborate across architecture, verification, physical implementation and integration teams.
• Contribute to continuous improvement of engineering processes and design methodologies.

Skills

RTL design

FPGA design

ASIC design

Verilog

SystemVerilog

High-throughput processing

Synthesis & timing analysis

EDA tools

Technical documentation

Agile hardware development

Tools

Verilog

SystemVerilog

EDA tools

PCIe

Job description

Spectrum IT Recruitment is seeking an experienced Senior Design Engineer to help develop cutting-edge communications technology for global connectivity. The role focuses on next‑generation 5G non‑terrestrial networks and satellite‑based systems, taking designs from architecture to validation on space‑qualified hardware platforms.

You will design high‑performance RTL for FPGA/ASIC targets, optimise for throughput and power, and collaborate across multiple engineering teams within an Agile