FPGA Engineer

SoCode Recruitment; Cambridge; Hybrid; GBP 54,000 - 90,000; Full time

Benefits offered by this job

Bonus

Healthcare

Enhanced pension

Job summary

SoCode Recruitment in Cambridge is seeking an FPGA Engineer focused on FPGA logic for controller boards, from design through verification and maintenance. The role is VHDL-based, targeting Xilinx Artix-7 devices in Vivado, with state machine design and low-level driver work.

You will work hands-on in a hybrid Cambridge environment (3-4 days on site), perform testing with scopes and logic analysers, and contribute to timing closure, constraints, and documentation.

Qualifications

• Solid VHDL experience on Xilinx devices and full Vivado flow experience (constraints, synthesis, place & route, timing closure, bitstream generation).
• Hands-on experience with serial protocols I²C, SPI, UART, including timing and edge-case handling.

Responsibilities

• Write and implement VHDL for Xilinx Artix-7 FPGAs in Vivado, following coding standards and design reviews.
• Design clean, deterministic state machines to sequence and control hardware interfaces.
• Build driver logic for serial interfaces (I²C, SPI; UART optional), including initialization, transactions and edge cases.
• Develop self-checking test benches, run simulations, and document verification processes.
• Bring boards up in the lab and validate them with logic analysers and oscilloscopes, debugging timing or constraint issues.
• Handle timing constraints (XDC), clocking, resets and CDC analysis through timing closure and bitstream generation.
• Contribute to requirements gathering, module specs, design reviews, and integration with wider system.
• Maintain configuration under version control and write documentation (specs, interfaces, test plans, release notes).

Skills

VHDL

Xilinx FPGA

Vivado flow

I2C

SPI

UART

Test benches

Timing analysis

Tools

Vivado

Xilinx Artix-7

Job description

Up to £90k DOE + bonus, healthcare, enhanced pension, etc.

Cambridge (Hybrid) | 3-4 days on site

Our client is looking for an FPGA Engineer to strengthen their permanent team based out of Cambridge.

You'll take ownership of FPGA logic for the controller boards that sit at the heart of the company's hardware, from design through to verification and ongoing maintenance. The work is VHDL-based, targeting Xilinx Artix-7 parts in Vivado, and spans state machine design, low-level driver work (I²C, SPI), test bench development and hands-on hardware testing.

Note that this sits at the discrete-logic and embedded-interfaces level rather than SoC development.

What you'll be doing:

• Writing and implementing VHDL for Xilinx Artix-7 FPGAs in Vivado, following coding standards and taking part in design reviews.
• Designing clean, deterministic state machines to sequence and control hardware interfaces.
• Building driver logic for serial interfaces such as I²C and SPI (UART a plus) - handling initialisation, transactions and error/edge cases.
• Developing self-checking test benches, running simulations, and documenting the verification process.
• Bringing boards up in the lab and validating them with logic analysers and oscilloscopes, debugging as issues arise.
• Handling timing constraints (XDC), clocking, resets and CDC analysis through to timing closure and bitstream generation.
• Feeding into requirements gathering, module-level specs and design reviews, and supporting integration with the wider system.
• Keeping configuration under version control (SVN) and writing up documentation - specs, interface descriptions, test plans, release notes.

What we're looking for:

• Solid, proven VHDL experience on Xilinx devices, and comfortable across the full Vivado flow - constraints, synthesis, place & route, timing closure, bitstream generation.
• Hands-on experience with serial protocols (I²C, SPI, ideally UART too), including the trickier bus arbitration, timing and edge-case scenarios.
• Ability to write self-checking test benches and run simulations (Vivado simulator or similar).
• Comfortable in the lab - bringing up boards, using scopes/logic analysers, and chasing down timing or constraint issues.
• Good grasp of CDC, metastability, reset strategy and synchronous design principles more broadly.
• A strong documenter and communicator who's equally happy working solo or as part of a cross-functional team

Unfortunately sponsorship is not available for this role.