Senior FPGA Architect: Ultra-Low Latency Systems

Platform Recruitment; Cambridge; On-site; GBP 70,000 - 100,000; Full time

Job summary

Platform Recruitment is seeking a Senior FPGA Engineer in Cambridge to oversee RTL design on ultra-low-latency platforms. You will architect RTL on high-end FPGAs, drive verification environments, and collaborate with firmware, software and infrastructure teams to optimise full-stack performance.

Required 7+ years FPGA/RTL experience, SystemVerilog, and hands-on with Vivado or Quartus. Familiarity with AXI/PCIe/Ethernet interfaces is preferred.

Qualifications

• 7+ years FPGA/RTL design experience in timing-critical systems.
• Strong background in SystemVerilog, synthesis, timing closure and verification.
• Hands-on with Vivado/Quartus or equivalent toolchains.
• Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.

Responsibilities

• Architect RTL designs on high-end FPGAs (Xilinx / Intel).
• Perform simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems.
• Lead the definition of micro-architectures and verification environments.
• Drive technical excellence through mentorship and code reviews.
• Collaborate with firmware, software and infrastructure teams to optimise performance.

Skills

SystemVerilog

FPGA RTL design

C/C++ or Python

High-speed interfaces

Tools

Vivado

Quartus

Job description

Platform Recruitment is seeking a Senior FPGA Engineer in Cambridge to oversee RTL design on ultra-low-latency platforms. You will architect RTL on high-end FPGAs, drive verification environments, and collaborate with firmware, software and infrastructure teams to optimise full-stack performance.

Required 7+ years FPGA/RTL experience, SystemVerilog, and hands-on with Vivado or Quartus. Familiarity with AXI/PCIe/Ethernet interfaces is preferred.