Senior digital IC design Engineer

Neuranics; Glasgow; On-site; GBP 60,000 - 80,000; Full time

Job summary

A fast-growing fabless semiconductor startup in Glasgow is seeking an RTL SoC Architect to lead the design of next-generation System-on-Chip platforms. In this role, you'll integrate Bluetooth technology and collaborate with experts to create scalable designs. Join us at the forefront of quantum-classical SoC innovation and make an impact in wearable technology and human-machine interfaces.

Qualifications

• Strong experience in RTL design of SoCs and IPs.
• Expertise in Bluetooth integration and low-power wireless protocols.

Responsibilities

• Design and integrate digital IP blocks using Verilog/SystemVerilog.
• Drive SoC-level verification (UVM/formal/assertions) and chip bring-up.

Skills

RTL design

Bluetooth integration

Scripting

Tools

Cadence

Job description

6 days ago Be among the first 25 applicants

Pioneering the next wave ofmagnetic sensingandquantum SoCs

Neuranics is a fast-growingfabless semiconductor startupbased in Glasgow, building transformativeTunnelling Magnetoresistance (TMR)sensor technology that powers the future ofwearables,XR, andhuman-machine interfaces.

As we push the limits of what’s possible inmagnetic and quantum sensing, we’re looking for a forward-thinkingRTL SoC Architectto lead the digital architecture and implementation of ournext-generation System-on-Chip (SoC)platforms—includingBluetooth integrationfor wireless communication.

Your Role:

You’ll be responsible for RTL design, IP integration, and verification of custom ASICs for ultra-low-power SoCs. These systems integrateembedded ARM cores, memory, Bluetooth modules, andanalog/mixed-signal front ends. You'll collaborate with analog, layout, and RF experts to architect scalable, silicon-proven designs.

What You’ll Do:

• Design and integrate digital IP blocks using Verilog/SystemVerilog
• Architect and implement Bluetooth interface IPs and protocol handling
• Work with embedded CPUs (ARM), memories, and AMBA (AHB/APB) interconnects
• Define SDC/UPF constraints and own synthesis, PnR, STA, and RTL-GDSII flow
• Drive SoC-level verification (UVM/formal/assertions) and chip bring-up
• Partner with Tier 1 consumer and semiconductor companies on cutting-edge projects

What We’re Looking For:

• Strong experience in RTL design of SoCs and IPs
• Expertise in Bluetooth integration and low-power wireless protocols
• Familiarity with CPU/DSP/FPU subsystems, SystemRDL, IP-XACT
• Proficiency in scripting (Python, TCL, Perl) and EDA tools (Cadence preferred)
• A passion for building game-changing silicon in emerging markets

Location: Glasgow (Onsite)

Join us at the frontier of quantum-classical SoC innovation.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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