Senior/Principal Physical Design Engineer - AI Accelerators

Fractile; Tottenham; On-site; GBP 90,000 - 150,000; Full time

Benefits offered by this job

Equity ownership

Private medical, dental & vision

Pension plan

25 days holiday + bank holidays

Job summary

Fractile is seeking a highly skilled Senior/Principal Physical Design Engineer to drive end-to-end ASIC/SoC physical implementations. You will collaborate with RTL, architecture, and process teams to optimize performance, power, and area while ensuring manufacturability.

The role requires 8+ years in physical design for advanced nodes, deep knowledge of DRC/LVS, and expertise with Cadence Innovus and related tools. A strong scripting background and excellent teamwork are essential.

Qualifications

• 8+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.

Responsibilities

• Drive the physical implementation of ASIC/SoC designs including floorplanning, placement, CTS, routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve best PPA metrics.
• Perform power planning and analysis addressing IR drop and electromigration.
• Ensure DRC, LVS, and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test structures.
• Develop flows in Cadence Innovus, Synopsys Fusion Compiler, and Mentor Calibre.

Skills

Physical design

ASIC/SoC knowledge

Scripting (TCL, Python, Perl)

Timing closure

Power integrity

Collaboration & communication

HPC/AI accelerators

High-performance computing experience

Education

Bachelor/Master/PhD in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Mentor Calibre

Job description

Fractile is seeking a highly skilled Senior/Principal Physical Design Engineer to drive end-to-end ASIC/SoC physical implementations. You will collaborate with RTL, architecture, and process teams to optimize performance, power, and area while ensuring manufacturability.

The role requires 8+ years in physical design for advanced nodes, deep knowledge of DRC/LVS, and expertise with Cadence Innovus and related tools. A strong scripting background and excellent teamwork are essential.